KSZ8041 Hynix Semiconductor, KSZ8041 Datasheet - Page 5

• Manufacturer Part Number: KSZ8041
• Manufacturer: Hynix Semiconductor

Rev. 0.04 /Jul. 2006
PIN DESCRIPTION
(LDQS,UDQS)
V
/RAS, /CAS, /
(LDM,UDM)
DDQ
V
A0 ~ A11
BA0, BA1
DD
CK, /CK
V
PIN
DQS
CKE
/CS
WE
DM
DQ
NC
REF
/ V
/ V
SS
SSQ
Supply
Supply
Supply
TYPE
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
NC
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for
SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output dis-
able. CKE must be maintained high throughout READ and WRITE accesses. Input buff-
ers, excluding CK, /CK and CKE are disabled during POWER DOWN. Input buffers,
excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will
detect an LVCMOS LOW level after V
Chip Select: Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when Chip Select is registered high. Chip Select provides for exter-
nal bank selection on systems with multiple banks. Chip Select is considered part of the
command code.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or
PRECHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a precharge
command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0,
BA1. The address inputs also provide the op code during a MODE REGISTER SET com-
mand. BA0 and BA1 define which mode register is loaded during the MODE REGISTER
SET command (MRS or EMRS).
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. Although DM pins are input only, the DM loading matches the
DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM cor-
responds to the data on DQ8-Q15.
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. For the x16, LDQS corresponds to
the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.
Data input / output pin: Data bus
Power supply for internal circuits and input buffers.
Power supply for output buffers for noise immunity.
Reference voltage for inputs for SSTL interface.
No connection.
DESCRIPTION
DD
is applied.
HY5DU281622FT(P) Series
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