KSZ8041 Hynix Semiconductor, KSZ8041 Datasheet - Page 10

• Manufacturer Part Number: KSZ8041
• Manufacturer: Hynix Semiconductor

Rev. 0.04 /Jul. 2006
POWER-UP SEQUENCE AND DEVICE INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those
specified may result in undefined operation. Power must first be applied to V
(and to the system VTT). VTT must be applied after V
age to the device. V
Except for CKE, inputs are not recognized as valid until after V
LVCMOS LOW level after V
guarantee that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal oper-
ation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR
SDRAM requires a 200us delay prior to applying an executable command.
Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED
MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE
REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating
parameters. After the DLL reset, t
ter set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command
for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting
the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.
1.
2.
3.
4.
5.
6.
7.
8.
• V
• VTT is limited to 1.44V (reflecting V
• V
• If the above criteria cannot be met by the system design, then the following sequencing and voltage relation-
Apply power - V
MOS low state. (All the other input pins may be undefined.)
Start clock and maintain stable clock for a minimum of 200usec.
After stable power and clock, apply NOP condition and take CKE high.
Issue Extended Mode Register Set (EMRS) to enable DLL.
Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200
cycles(t
Issue Precharge commands for all banks of the device.
Issue 2 or more Auto Refresh commands.
Issue a Mode Register Set command to initialize the mode register with bit A8 = Low
ship must be adhered to during power up.
DD
REF
Voltage description
XSRD
and V
tracks V
V
) of clock are required for locking DLL)
V
VTT
DDQ
DDQ
REF
DD
DDQ
REF
are driven from a single power converter output.
, V
/2.
can be applied anytime after V
DDQ
DD
, VTT, V
is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to
XSRD
After or with V
After or with V
After or with V
(DLL locking time) should be satisfied for read command. After the Mode Regis-
REF
Sequencing
DDQ
in the following power up sequencing and attempt to maintain CKE at LVC-
(max)/2 + 50mV V
DDQ
DDQ
DD
DDQ
DDQ
to avoid device latch-up, which may cause permanent dam-
REF
, but is expected to be nominally coincident with VTT.
is applied. CKE is an SSTL_2 input, but will detect an
Voltage relationship to avoid latch-up
REF
variation + 40mV VTT variation.
< V
< V
< V
DD
HY5DU281622FT(P) Series
DDQ
DDQ
DD
, then to V
+ 0.3V
+ 0.3V
+ 0.3V
DDQ
, and finally to VREF
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