ADS8320E Burr-Brown Corporation, ADS8320E Datasheet - Page 8

• Manufacturer Part Number: ADS8320E
• Description: 16-Bit/ High-Speed/ 2.7V to 5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

THEORY OF OPERATION
The ADS8320 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a 0.6
CMOS process. The architecture and process allow the
ADS8320 to acquire and convert an analog signal at up to
100,000 conversions per second while consuming less than
4.5mW from +V
The ADS8320 requires an external reference, an external
clock, and a single power source (V
ence can be any voltage between 500mV and V
of the reference voltage directly sets the range of the analog
input. The reference input current depends on the conversion
rate of the ADS8320.
The external clock can vary between 24kHz (1kHz through-
put) and 2.4MHz (100kHz throughput). The duty cycle of
the clock is essentially unimportant as long as the minimum
high and low times are at least 200ns (V
greater). The minimum clock frequency is set by the leakage
on the capacitors internal to the ADS8320.
The analog input is provided to two input pins: +In and –In.
When a conversion is initiated, the differential input on these
pins is sampled on the internal capacitor array. While a
conversion is in progress, both inputs are disconnected from
any internal function.
The digital result of the conversion is clocked out by the
DCLOCK input and is provided serially, most significant bit
first, on the D
D
is no pipeline delay. It is possible to continue to clock the
ADS8320 after the conversion is complete and to obtain the
serial data least significant bit first. See the digital timing
section for more information.
ANALOG INPUT
The +In and –In input pins allow for a differential input
signal. Unlike some converters of this type, the –In input is
not re-sampled later in the conversion cycle. When the
converter goes into the hold mode, the voltage difference
between +In and –In is captured on the internal capacitor
array.
The range of the –In input is limited to –0.1V to +1V (–0.1V
to +0.5V when using a 2.7V supply). Because of this, the
differential input can be used to reject only small signals that
are common to both inputs. Thus, the –In input is best used
to sense a remote signal ground that may move slightly with
respect to the local ground potential.
The input current on the analog inputs depends on a number
of factors: sample rate, input voltage, source impedance, and
power-down mode. Essentially, the current into the ADS8320
charges the internal capacitor array during the sample pe-
OUT
pin is for the conversion currently in progress—there
®
OUT
ADS8320
CC
pin. The digital data that is provided on the
.
CC
). The external refer-
CC
CC
. The value
= 2.7V or
8
riod. After this capacitance has been fully charged, there is
no further input current. The source of the analog input
voltage must be able to charge the input capacitance (45pF)
to a 16-bit settling level within 4.5 clock cycles. When the
converter goes into the hold mode or while it is in the power-
down mode, the input impedance is greater than 1G .
Care must be taken regarding the absolute analog input
voltage. To maintain the linearity of the converter, the –In
input should not drop below GND – 100mV or exceed
GND + 1V. The +In input should always remain within the
range of GND – 100mV to V
ranges, the converter’s linearity may not meet specifications.
To minimize noise, low bandwidth input signals with low-
pass filters should be used.
REFERENCE INPUT
The external reference sets the analog input range. The
ADS8320 will operate with a reference in the range of
500mV to V
this.
As the reference voltage is reduced, the analog voltage
weight of each digital output code is reduced. This is often
referred to as the Least Significant Bit (LSB) size and is
equal to the reference voltage divided by 65,536. This means
that any offset or gain error inherent in the A/D converter
will appear to increase, in terms of LSB size, as the reference
voltage is reduced.
The noise inherent in the converter will also appear to
increase with lower LSB size. With a +5V reference, the
internal noise of the converter typically contributes only 1.5
LSB peak-to-peak of potential error to the output code.
When the external reference is 500mV, the potential error
contribution from the internal noise will be 10 times larger—
15 LSBs. The errors due to the internal noise are gaussian in
nature and can be reduced by averaging consecutive conver-
sion results.
For more information regarding noise, consult the typical
performance curve “Peak-to-Peak Noise vs Reference Volt-
age.” Note that the Effective Number of Bits (ENOB) figure
is calculated based on the converter’s signal-to-(noise +
distortion) ratio with a 1kHz, 0dB input signal. SINAD is
related to ENOB as follows:
With lower reference voltages, extra care should be taken to
provide a clean layout including adequate bypassing, a clean
power supply, a low-noise reference, and a low-noise input
signal. Because the LSB size is lower, the converter will also
be more sensitive to external sources of error such as nearby
digital signals and electromagnetic interference.
CC
SINAD = 6.02 • ENOB + 1.76
. There are several important implications of
CC
+ 100mV. Outside of these