ADS7835E Burr-Brown Corporation, ADS7835E Datasheet - Page 8

• Manufacturer Part Number: ADS7835E
• Description: 12-Bit/ High-Speed/ Low Power Sampling ANALOG-TO-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

FIGURE 2. Serial Data and Clock Timing.
EXTERNAL REFERENCE
The internal reference is connected to the V
internal buffer via a 10k series resistor. Thus, the reference
voltage can easily be overdriven by an external reference
voltage. The voltage range for the external voltage is 2.3V
to 2.9V, corresponding to an analog input range of 2.3V to
2.9V in both cases.
While the external reference will not source significant
current into the V
series resistor that is terminated into the 2.5V internal
reference (the exact value of the resistor will vary up to
still be bypassed to ground with at least a 0.1 F ceramic
capacitor (placed as close to the ADS7835 as possible). The
reference will have to be stable with this capacitive load.
Depending on the particular reference and A/D conversion
speed, additional bypass capacitance may be required, such
as the 2.2 F tantalum capacitor shown in Figure 1.
Reasons for choosing an external reference over the internal
reference vary, but there are two main reasons. One is to
achieve a given input range. The other is to provide greater
stability over temperature. (The internal reference is typi-
cally 20ppm/ C which translates into a full-scale drift of
roughly one output code for every 12 C. This does not take
into account other sources of full-scale drift.) If greater
stability over temperature is needed, then an external refer-
ence with lower temperature drift will be required.
DIGITAL INTERFACE
Figure 2 shows the serial data timing and Figure 3 shows the
basic conversion timing for the ADS7835. The specific
timing numbers are listed in Table I. There are several
important items in Figure 3 which give the converter addi-
tional capabilities over typical 8-pin converters. First, the
transition from sample mode to hold mode is synchronous to
the falling edge of CONV and is not dependent on CLK.
Second, the CLK input is not required to be continuous
during the sample mode. After the conversion is complete,
30% from part to part). In addition, the V
®
ADS7835
REF
pin, it does have to drive the 10k
DATA
CLK
REF
t
CKH
REF
pin and to the
pin should
t
CKP
t
CKL
t
CKDS
8
the CLK may be kept LOW or HIGH.
The asynchronous nature of CONV to CLK raises some
interesting possibilities, but also some design consider-
ations. Figure 3 shows that CONV has timing restraints in
relation to CLK (t
are violated (which could happen if CONV is completely
asynchronous to CLK), the converter will perform a conver-
sion correctly, but the exact timing of the conversion is
indeterminate. Since the setup and hold time between CONV
and CLK has been violated in this example, the start of
conversion could vary by one clock cycle. (Note that the
start of conversion can be detected by using a pull-up
resistor on DATA. When DATA drops out of high imped-
ance and goes LOW, the conversion has started and that
Note: (1) This timing is not required under some situations. See text for more information.
TABLE I. Timing Specifications (T
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CONV
t
t
CKDH
CKDS
t
CKCH
CKCS
CKDE
CKDD
CKPD
CVHD
CVPU
CVDD
CVPD
t
t
t
CKSP
CVSP
ACQ
CKP
CKH
CVH
DRP
CKL
CVL
Clock Falling to Power-Down Mode
Clock Falling to Next Data Valid
CONV Changing State to DATA
CONV Setup to Clock Falling
Clock Falling to DATA Enabled
CONV Hold after Clock Falls
CONV Rising to Sample Mode
CONV Rising to Full Power-up
C
Clock Falling to Sample Mode
CONV Falling to Start of CLK
Clock Falling to Current Data
CONV Falling to Hold Mode
(for hold droop < 0.1 LSB)
CONV Changing State to
LOAD
Clock Falling to DATA
Bit No Longer Valid
Power-Down Mode
Conversion Time
Acquisition Time
High Impedance
(Aperture Delay)
High Impedance
DESCRIPTION
Clock Period
CONV HIGH
CKCH
Clock HIGH
CONV LOW
Clock LOW
= 30pF).
t
CKDH
and t
CKCS
(1)
(1)
). However, if these times
1.625
MIN
350
125
50
50
40
40
10
10
5
A
= –40 C to +85 C,
TYP
15
30
20
70
50
50
70
50
5
5
5
MAX
5000
100
100
50
50
5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s