ADS1255IDB Burr-Brown Corporation, ADS1255IDB Datasheet - Page 6

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ADS1255IDB

Manufacturer Part Number
ADS1255IDB
Description
Very Low Noise/ 24-Bit Analog-to-Digital Converter
Manufacturer
Burr-Brown Corporation
Datasheet

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ADS1255
ADS1256
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
6
TIMING CHARACTERISTICS FOR FIGURE 1
(1) CLKIN = master clock period = 1/f CLKIN .
(2) DATA = output data period 1/f DATA .
(3) CS can be tied low.
(4) DOUT load = 20pF
SYMBOL
t 2H
t 2H
t 2L
t 10
t
t 11
t 1
t 1
t 3
t 4
t 5
t 6
t 7
t 8
t 9
DESCRIPTION
SCLK period
SCLK period
SCLK pulse width: high
SCLK pulse width: high
SCLK pulse width: low
CS low to first SCLK: setup time (3)
Valid DIN to SCLK falling edge: setup time
Valid DIN to SCLK falling edge: hold time
Delay from last SCLK edge for DIN to first SCLK rising edge for DOUT: RDATA, RDATAC,
RREG Commands
SCLK rising edge to valid new DOUT: propagation delay (4)
SCLK rising edge to DOUT invalid: hold time
Last SCLK falling edge to DOUT high impedance
NOTE: DOUT goes high impedance immediately when CS goes high
CS low after final SCLK falling edge
Final SCLK falling edge of command to first SCLK
Final SCLK falling edge of command to first SCLK
rising edge of next command.
DOUT
SCLK
DIN
CS
100k to DGND.
t
PARAMETER MEASUREMENT INFORMATION
3
t
4
t
Figure 1. Serial Interface Timing
1
t
5
RREG, WREG, RDATA
RDATAC, RESET, SYNC
RDATAC, STANDBY, SELFOCAL, SY-
SOCAL, SELFGCAL,
SYSGCAL, SELFCAL
t
6
t
t
2H
7
t
8
t
2L
t
10
t
9
t
11
Wait for DRDY to go low
MIN
200
200
50
50
50
24
4
0
0
6
0
4
MAX
10
50
10
9
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CLKIN (1)
DATA (2)
CLKIN
CLKIN
CLKIN
CLKIN
UNIT
DATA
ns
ns
ns
ns
ns
ns
ns
ns

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