ADS1255IDB Burr-Brown Corporation, ADS1255IDB Datasheet - Page 20

• Manufacturer Part Number: ADS1255IDB
• Description: Very Low Noise/ 24-Bit Analog-to-Digital Converter
• Manufacturer: Burr-Brown Corporation

ADS1255
ADS1256
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
5.76MHz, 7.68MHz, are the same. The digital filter will
attenuate high-frequency noise on the ADS1255/6 inputs
up to the frequency where the response repeats. If
significant noise on the inputs is present above this
frequency, make sure to remove with external filtering.
Fortunately, this can be done on the ADS1255/6 with a
simple RC filter, as shown in the Applications Section (see
Figure 25).
SETTLING TIME
The ADS1255/6 features a digital filter optimized for fast
settling. The settling time (time required for a step change
on the analog inputs to propagate through the filter) for the
different data rates is shown in Table 13. The following
sections highlight the single-cycle settling ability of the
filter and show various ways to control the conversion
process.
20
Figure 16. Frequency Response Out to 7.68MHz
Figure 17. Frequency Response Out to 7.68MHz
100
120
140
100
120
140
20
40
60
80
20
40
60
80
0
0
0
0
for Data Rate = 30kSPS
for Data Rate = 2.5SPS
1.92
1.92
Frequency (MHz)
Frequency (MHz)
3.84
3.84
5.76
5.76
f
f
f
f
D A T A
C L K I N
D A T A
C L K IN
= 2 .5 S P S
= 3 0 k S P S
= 7 .6 8 M H z
= 7 .6 8 M H z
7.68
7.68
Settling Time Using Synchronization
The SYNC/PDWN pin allows direct control of conversion
timing. Simply issue a Sync command or strobe the
SYNC/PDWN pin after changing the analog inputs (see
the Synchronization section for more information). The
conversion begins when SYNC/PDWN is taken high,
stopping the current conversion and restarting the digital
filter. As soon as SYNC/PDWN goes low, the DRDY
output goes high and remains high during the conversion.
After the settling time (t
data is available. The ADS1255/6 settles in a single
cycle—there is no need to ignore or discard data after
synchronization. Figure 18 shows the data retrieval
sequence following synchronization.
NOTE: f CLKIN = 7.68MHz.
SYNC/PDWN
Figure 18. Data Retrieval After Synchronization
AIN
P
−AIN
DRDY
DOUT
Table 13. Settling Time vs Data Rate
DIN
DATA RATE
N
30,000
15,000
(SPS)
7500
3750
2000
1000
500
100
2.5
60
50
30
25
15
10
5
18
), DRDY goes low, indicating that
t
18
SETTLING TIME (t 18 )
RDATA
100.18
200.18
400.18
10.18
16.84
20.18
33.51
40.18
66.84
(ms)
0.21
0.25
0.31
0.44
0.68
1.18
2.18
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Settled
Data