MAX5556 Maxim Integrated Products, MAX5556 Datasheet - Page 11

• Manufacturer Part Number: MAX5556
• Description: Low-Cost Stereo Audio DAC
• Manufacturer: Maxim Integrated Products

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LRCLK is the left/right clock input signal for the 3-wire
interface and sets the sample frequency (f
MAX5556, drive LRCLK low to direct data to OUTL or
LRCLK high to direct data to OUTR (Figure 4). The
MAX5556 accepts data at LRCLK audio sample rates
from 2kHz to 50kHz.
MCLK accepts the master clock signal from an external
clocking device and is used to derive internal clock fre-
quencies. Set the MCLK/LRCLK ratio to 256, 384, or
512 to achieve the internal serial clock frequencies list-
ed in Table 1. Table 2 details the MCLK/LRCLK ratios
for three sample audio rates.
The MAX5556 detects the MCLK/LRCLK ratio during
the initialization sequence by counting the number of
MCLK transitions during a single LRCLK period. MCLK,
SCLK, and LRCLK must be synchronous signals.
Table 1. Internal and External Clock
Frequencies
Table 2. MCLK/LRCLK Ratios
LRCLK
(kHz)
44.1
M C L K /L R C L K
= 2 5 6 O R 51 2
32
48
32 x f
CLOCK FREQUENCY
INTERNAL SERIAL
MCLK/LRCLK
S
11.2896
12.2880
8.1920
= 256
______________________________________________________________________________________
M C L K /L R C L K
Left/Right Clock Input (LRCLK)
48 x f
= 3 8 4
MCLK/LRCLK
MCLK (MHz)
S
12.2880
16.9344
18.4320
= 384
Master Clock (MCLK)
CLOCK FREQUENCY
EXTERNAL SERIAL
User defined
(Figure 4)
MCLK/LRCLK
16.3840
22.5792
24.5760
S
= 512
). On the
Low-Cost Stereo Audio DAC
The MAX5556 accepts data with an I
data format, accepting 16 or 24 bits of data. SDATA
accepts data in two’s complement format with the MSB
first. The MSB is valid on the second SCLK rising edge
after LRCLK transitions low to high or high to low
(Figure 4). Drive LRCLK low to direct data to OUTL.
Drive LRCLK high to direct data to OUTR. The number
of SCLK pulses with LRCLK high or low determines the
number of bits transferred per sample. If fewer than 24
bits of data are written, the remaining LSBs are set to 0.
If more than 24 bits are written, any bits after the LSB
are ignored.
The MAX5556 accepts up to 24 bits of data in external
serial clock mode or when the MCLK/LRCLK ratio is
384 (internal serial clock = 48 x f
clock mode. The DAC also accepts 16 bits of data in
internal serial clock mode when the MCLK/LRCLK ratio
is 256 or 512 (internal serial clock = 32 x f
Use an external lowpass analog filter to further reduce
harmonic images, noise, and spurs. The external analog
filter can be either active or passive depending upon
performance and design requirements. For example fil-
ters, see Figures 8 and 9 and the Applications
Information section. Careful attention should be paid
when selecting capacitors for audio signal path applica-
tions. NPO and C0G types are recommended as are alu-
minum electrolytics and low-ESR tantalum varieties. Use
of generic ceramic types is not recommended and may
result in degraded THD performance. Always consult
manufacturers’ data sheets and applications information.
Figure 8. Passive Component Analog Output Filter
MAX5556
MAX5556 I
OUTR
OUTL
100kΩ
100kΩ
2
S Left-Justified Data Format
External Analog Filter
R = 560Ω
R = 560Ω
C = 1.5nF
C = 1.5nF
S
) in internal serial
Data Formats
2
S left-justified
S
).
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