ADS-235 Datel, Inc., ADS-235 Datasheet - Page 3

• Manufacturer Part Number: ADS-235
• Description: Sampling A/D Converters
• Manufacturer: Datel, Inc.

FUNCTIONAL DESCRIPTION
The ADS-235, ADS-236 and ADS-237 are 12-bit fully
differential pipeline sampling A/D converters with digital error
correction. Referring to the Functional Block Diagram shown in
figure 1, figure 3.1 shows the circuit for the front end differential
in and out sample-and-hold (S/H). The switches are controlled
by an internal sampling clock which is a non-overlapping two
phase signal, Ø1 and Ø2, derived from the master sampling
clock. During the sampling phase, Ø1, the input signal is
POWER REQUIREMENTS
Footnotes:
Power Supply Ranges
Power Supply Currents
Power Dissipation
Offset Error Sensitivity, 5V±5%
Gain Error Sensitivity, 5V±5%
+5V Analog Supply, +AV
+5V Digital Supply, +DV
+3V Digital Supply, +DV
+5V Digital Supply, +DV
ADS-235, ADS-236
+AI
+DI
+DI
ADS-237
+AI
+DI
+DI
ADS-235
ADS-236
ADS-237
ADS-235
ADS-236, ADS-237
ADS-235
ADS-236, ADS-237
®
S
S
S
S
S
S
1
2
1
2
Analog Input,
3RD Stage
1ST Stage
2ND Stage
4TH Stage
For F
Differential Mode
Not specified
A/D CLK
VIN
Output
Data
S
step to settle to 12-bits accuracy
S
S
S
S
1
2
2
SN–1 HN–1
®
B2, N–2
MIN.
+4.75
+4.75
+4.75
+2.7
—
—
—
—
—
—
—
—
—
—
—
—
—
SN
B1, N–1
B1, N–1
B3, N–2
CLK off and Low
No missing codes
DN–3
HN
TYP.
±16
±16
300
300
325
30
46
13
46
17
B2, N–1
B4, N–2
5
5
3
5
1
2
2
SN+1
B1, N
B1, N
B3, N–1
MAX.
DN–2
+5.25
+5.25
+5.25
Figure 2A. Internal Timing Diagram
tLAT
+3.3
350
365
HN+1
—
—
—
—
—
—
—
—
—
—
—
B2, N
B4, N–1
SN+2
UNITS
Volts
Volts
Volts
Volts
mW
mW
LSB
LSB
LSB
LSB
mW
mA
mA
mA
mA
mA
mA
B1, N+1
B1, N+1
B3, N
HN+2
DN–1
B2, N+1
B4, N
3
SN+3
applied to the sampling capacitors, C
hold capacitors, C
falling edge of Ø1 the input signal is sampled on the bottom
plates of the sampling capacitors. In the next clock phase, Ø2,
the two bottom plates of the sampling capacitors are connected
together and the holding capacitors are switched to the op-amp
output nodes. The charge then redistributes between C
C
The sample and hold output is a fully differential representation
of the sampled analog input. The circuit not only performs the
sample-hold function but will also convert a single-ended input
to a fully differential output. During the sampling phase, the V
pins see only the on resistance of a switch and C
values of these components result in a typical full power input
bandwidth of 100MHz for the converters.
As illustrated in the Functional Block Diagram, figure 1, and the
Internal Timing Diagram, figure 2A, three identical pipeline
sub-converter stages, each containing a four-bit flash converter
and a four-bit multiplying digital-to-analog converter, follow the
S/H with the fourth stage being a four-bit flash converter. Each
converter stage in the pipeline will be sampling in one clock
phase and amplifying in the other clock phase. Each sub-
converter clock signal is offset by 180 degrees from the
previous stage clock signal resulting in alternate stages in the
pipeline performing the same operation.
The four-bit output of each of the sub-converter stages is used
by the error correction logic. The output of each stage is input
to a digital delay line which is controlled by the internal
sampling clock. The function of the delay line is to align the
digital outputs in time of the three identical stages with the
output of the fourth stage flash converter before applying the
sixteen bit result to the error correction logic. The error
correction logic uses the supplementary bits to correct any
error that may exist before generating the final twelve-bit digital
data output.
Due to the pipeline nature of this converter, the digital data
representing an analog input sample is output to the digital
H
B1, N+2
B3, N+1
DN
HN+3
completing one sample and hold cycle.
B4, N+1
B2, N+2
SN+4 HN+4 SN+5 HN+5 SN+6 HN+6
ADS-235, ADS-236, ADS-237
B1, N+3
B3, N+2
DN+1
Notes: 1. SN: N-th sampling period.
H
B4, N+2
B2, N+3
, are discharged to analog ground. At the
2. HN: N-th holding period.
3. BM, N: M-th stage digital output corresponding to N-th sampled input.
4. DN: Final data output corresponding to N-th sampled input.
B1, N+4
B3, N+3
DN+2
B4, N+3
B2, N+4
B1, N+5
B3, N+4
DN+3
S
. At the same time the
B4, N+4
B2, N+5
S
. The small
S
and
IN