MAX1497 Maxim, MAX1497 Datasheet - Page 6

• Manufacturer Part Number: MAX1497
• Description: 3.5- and 4.5-Digit / Single-Chip ADCs with LED Drivers and C Interface
• Manufacturer: Maxim

3.5- and 4.5-Digit, Single-Chip ADCs with LED
Drivers and µC Interface
TIMING CHARACTERISTICS (Notes 11, 12, Figure 8)
(AV
C
Typical values are at T
Note 1: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error and
Note 2: Offset calibrated. See OFFSET_CAL1 and OFFSET_CAL2 (MAX1499 only) in the On-Chip Registers section.
Note 3: Offset nulled.
Note 4: Offset drift error is eliminated by recalibration at the new temperature.
Note 5: The input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pair.
Note 6: V
Note 7: Measured at DC by changing the power-supply voltage from 2.7V to 5.25V and measuring the effect on the conversion
Note 8: CLK and SCLK are disabled.
Note 9: LED drivers are disabled.
Note 10: Power-supply currents are measured with all digital inputs at either GND, DV
Note 11: All input signals are specified with t
Note 12: See the serial-interface timing diagrams.
6
SCLK Operating Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
DIN to SCLK Setup
DIN to SCLK Hold
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Fall to DOUT Valid
CS Rise to DOUT Disable
CS Fall to DOUT Enable
REF+
DD
_______________________________________________________________________________________
= DV
= C
offset error.
AIN+ and REF+ only.
error with external reference. PSRR at 50Hz and 60Hz exceeds 120dB with filter notches at 50Hz and 60Hz (Figure 2).
DV
PARAMETER
AIN
REF-
DD
DD
+ or V
, unless otherwise noted.
= V
= 0.1µF, C
DD
AIN
= +2.7V to +5.25V, GND = 0, GLED = 0, V
A
- = -2.2V to +2.2V. V
= +25°C, unless otherwise noted.)
VNEG
= 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at T
SYMBOL
f
t
SCLK
t
t
t
t
CSH
t
t
CSS
t
t
DO
CH
DH
CL
DS
TR
DV
REF
RISE
+ or V
= t
C
C
C
LOAD
LOAD
LOAD
FALL
REF
- = -2.2V to +2.2V. All input structures are identical. Production tested on
= 5ns (10% to 90% of DV
= 50pF, Figures 13, 14
= 50pF, Figures 13, 14
= 50pF, Figures 13, 14
CONDITIONS
LED
= +2.7V to +5.25V, V
DD
DD
, or V
) and are timed from a voltage level of 50% of
DD
REF+
and with the device in internal-clock mode.
- V
MIN
100
100
50
50
REF-
0
0
0
= 2.048V (external reference)
TYP
A
MAX
120
120
120
= T
4.2
MIN
to T
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX
.