L64733C LSI Logic Corporation, L64733C Datasheet - Page 16

• Manufacturer Part Number: L64733C
• Description: Tuner And Satellite Receiver Chipset Data Sheet 2/01
• Manufacturer: LSI Logic Corporation

Phase-Locked Loop (PLL) Interface
16
XOIN
XOOUT
The internal PLL generates the signals to operate the ADC,
Demodulator, and FEC modules.
LCLK
LP2
PCLK
PLLAGND
PLLVDD
PLLVSS
L64733C/L64734 Tuner and Satellite Receiver Chipset
Crystal Oscillator In
The XOIN pin provides a crystal oscillator or external
reference clock input. Normally, a 15 MHz crystal is
connected to the XOIN pin.
Crystal Oscillator Out
The XOOUT pin is the crystal oscillator output pin.
Decimated Clock Output
The L64734 internal clock generation module generates
the LCLK signal. LCLK is derived from CLK by dividing
by the value of the CLK_DIV2 register parameter.
Input to VCO
The LP2 signal is the input to the internal
voltage-controlled oscillator. Normally, it is connected to
the output of an external RC filter circuit.
PLL Clock Output
The L64734 internal PLL clock synthesis module
generates the PCLK signal. The reference crystal
connected between the XOIN and XOOUT pins drives
the PLL. The PLL clock synthesis module can be
configured to generate a PCLK rate that is appropriate for
all data rates.
PLL Analog Ground
PLLAGND is the analog ground pin for the PLL module
and normally is connected to the system ground plane.
PLL Power
PLLVDD is the power supply pin for the PLL module and
normally is connected to the system power (V
PLL Ground
PLLVSS is the ground pin for the PLL module and
normally is connected to the system ground plane.
DD
) plane.
Output
Output
Output
Input
Input
Input
Input
Input