WM8746 Wolfson Microelectronics plc, WM8746 Datasheet - Page 24

• Manufacturer Part Number: WM8746
• Description: 24-bit, 192khz 6-channel Dac With Volume Control
• Manufacturer: Wolfson Microelectronics plc

WM8746
w
0000010
DAC Control
0000011
Interface
Control
REGISTER
ADDRESS
BIT
5:4
8:6
8:5
1:0
0
1
2
2
3
3
4
DEEMPH
FMT[1:0]
WL[1:0]
PHASE
LABEL
PWDN
PL[3:0]
MUTE
ATC
BCP
LRP
IZD
DEFAULT
1001
000
00
10
0
0
0
0
0
0
0
Left and Right DACs soft mute control
De-emphasis Control
Left and Right DACs Power-down Control
Attenuator Control
Infinite zero detection circuit control and automute control
DAC Output Control
PL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
Interface format select
LRCIN Polarity or LRCIN Phase
Left Justified / Right Justified / I
0: Standard LRCIN Polarity
1: Inverted LRCIN Polarity
BCKIN Polarity
Input Word Length
Controls the output phase of the three stereo channels
0: Normal Response (see Figure 14 - Figure 17)
1: De-emphasis Response (see Figure 18 - Figure 23)
00: right justified mode
01: left justified mode
10: I
11: DSP Mode A or B
0: No Mute
1: Mute
0: All DACs running, output is active
1: All DACs in power saving mode, output muted
0: All DACs use attenuations as programmed.
1: Right chan. DACs use corresponding left DAC attenuations
0: Infinite zero detect disabled
1: Infinite zero detect enabled
0: Normal (DIN[2:0] and LRCIN sampled on rising edge)
1: Inverted (DIN[2:0] and LRCIN sampled on falling edge)
00: 16-bit Mode
01: 20-bit Mode
10: 24-bit Mode
11: 32-bit Mode (not supported in right justified mode)
Bit 6 reverses the phase of data output on OUT0L/R.
Bit 7 reverses the phase of data output on OUT1L/R.
Bit 8 reverses the phase of data output on OUT2L/R.
2
S mode
Left
Output
Mute
Left
Right
(L+R)/2
Mute
Left
Right
(L+R)/2
Right
Output
Mute
Mute
Mute
Mute
Left
Left
Left
Left
DESCRIPTION
2
S
PL[3:0]
1000
1001
1010
1011
1100
1101
1110
1111
DSP Mode
0: DSP Mode A
1: DSP Mode B
PD, October 2008, Rev 4.2
Mute
Left
Left
Output
Right
(L+R)/2
Mute
Left
Right
(L+R)/2
Production Data
Right
Output
Right
Right
Right
Right
(L+R)/2
(L+R)/2
(L+R)/2
(L+R)/2
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