WM8746 Wolfson Microelectronics plc, WM8746 Datasheet - Page 19

• Manufacturer Part Number: WM8746
• Description: 24-bit, 192khz 6-channel Dac With Volume Control
• Manufacturer: Wolfson Microelectronics plc

WM8746
Table 7 Attenuation Register Map
Note:
The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-latch but not applied to the
relevant DAC. If UPDATE=1, all pre-latched values will be applied from the next input sample. Writing to MASTA[7:0]
overwrites any values previously sent to L0A[7:0], L1A[7:0], L2A[7:0], R0A[7:0], R1A[7:0], R2A[7:0].
w
0000000
Attenuation
DACL0
0000001
Attenuation
DACR0
0000100
Attenuation
DACL1
0000101
Attenuation
DACR1
0000110
Attenuation
DACL2
0000111
Attenuation
DACR2
0001000
Master
Attenuation
(all channels)
REGISTER
ADDRESS
BIT
7:0
7:0
7:0
7:0
7:0
7:0
7:0
8
8
8
8
8
8
8
MASTA[7:0]
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
R0A[7:0]
R1A[7:0]
R2A[7:0]
L0A[7:0]
L1A[7:0]
L2A[7:0]
ATTENUATION CONTROL
Each DAC channel can be attenuated digitally before being applied to the digital filter. Attenuation is
0dB by default but can be set between 0 and 127.5dB in 0.5dB steps using the 8 Attenuation control
bits. All attenuation registers are double latched allowing new values to be pre-latched to several
channels before being updated synchronously. Setting the UPDATE bit on any attenuation write will
cause all pre-latched values to be immediately applied to the DAC channels. A master attenuation
register is also included, allowing all attenuations to be set to the same value in a single write.
LABEL
Not latched
Not latched
Not latched
Not latched
Not latched
Not latched
Not latched
11111111
11111111
11111111
11111111
11111111
11111111
11111111
DEFAULT
(0dB)
(0dB)
(0dB)
(0dB)
(0dB)
(0dB)
(0dB)
Attenuation data for DACL0 in 0.5dB steps, see Table 8.
Controls simultaneous update of all Attenuation Latches
Attenuation data for DACR0 in 0.5dB steps, see Table 8.
Controls simultaneous update of all Attenuation Latches
Attenuation data for DACL1 in 0.5dB steps, see Table 8.
Controls simultaneous update of all Attenuation Latches
Attenuation data for DACR1 in 0.5dB steps, see Table 8.
Controls simultaneous update of all Attenuation Latches
Attenuation data for DACL2 in 0.5dB steps, see Table 8.
Controls simultaneous update of all Attenuation Latches
Attenuation data for DACR2 in 0.5dB steps, see Table 8.
Controls simultaneous update of all Attenuation Latches
Attenuation data for all channels in 0.5dB steps, see Table 8.
Controls simultaneous update of all Attenuation Latches
0: Store DACL0 in intermediate latch (no change to output)
1: Store DACL0 and update attenuation on all channels.
0: Store DACR0 in intermediate latch (no change to output)
1: Store DACR0 and update attenuation on all channels.
0: Store DACL1 in intermediate latch (no change to output)
1: Store DACL1 and update attenuation on all channels.
0: Store DACR1 in intermediate latch (no change to output)
1: Store DACR1 and update attenuation on all channels.
0: Store DACL2 in intermediate latch (no change to output)
1: Store DACL2 and update attenuation on all channels.
0: Store DACR2 in intermediate latch (no change to output)
1: Store DACR2 and update attenuation on all channels.
0: Store MASTA[7:0] in all intermediate latches (no change to
1: Store MASTA[7:0] and update attenuation on all channels.
output)
DESCRIPTION
PD, October 2008, Rev 4.2
Production Data
19