HFA3861AIN Intersil Corporation, HFA3861AIN Datasheet - Page 25

• Manufacturer Part Number: HFA3861AIN
• Description: Processor, Direct Sequence Spread Spectrum Base band Processor
• Manufacturer: Intersil Corporation

Bits 5:4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bits 2:0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SFD Time-out values
00 = 56µs
01 = 64µs
10 = 128µs
11 = 144µs
MD_RDY control
0 = After CRC16
1 = After SFD
Force F. O. E. in all antenna diversity timelines.
Antenna choice for Receiver when single antenna acquisition is selected
0 = Antenna select pin low
1 = Antenna select pin high
Single or dual antenna acquire
0 = dual antenna for diversity acquisition
1 = single antenna
Continuous internal RX 22 and 44MHz clocks; (Only Reset active will stop) overrides CR10 bit 6. This bit should be loaded to
a “1” then to a “0” during initial register loading to ensure receiver initialization.
A/D input coupling
0 = DC
1 = AC (external bias network required)
TX filter / CMF weight select
0 = US
1 = Japan
Ping Pong Differential Encode enable
0 = disabled Ping Pong Differential encoding
1 = normal Ping Pong Differential encoding
CCA mode
0 = normal CCA. CCA will immediately respond to changes in ED, CS1, and SQ1 as configured
1 = Sampled CCA. CCA will update once per slot (20µs), will be valid at 19.8µs or 15.8µs as determined by CR9 bit 7.
Precursor value in CIR estimate
All DAC and A/D clock source control
0 = normal internal clocks
1 = clock via SDI pin
TX DAC clock
0 = enable
1 = disable
RX DAC clock
0 = enable
1 = disable
I DAC clock
0 = enable
1 = disable
Q DAC clock
0 = enable
1 = disable
RF A/D clock
0 = enable
1 = disable
I A/D clock
0 = enable
1 = disable
CONFIGURATION REGISTER 10 ADDRESS (14h) R/W RX CONFIGURE (Continued)
25
CONFIGURATION REGISTER 11 ADDRESS (16h) R/W RX-TX CONFIGURE
CONFIGURATION REGISTER 12 ADDRESS (18h) R/W A/D TEST MODES 1
HFA3861A