HFA3861AIN Intersil Corporation, HFA3861AIN Datasheet - Page 19

• Manufacturer Part Number: HFA3861AIN
• Description: Processor, Direct Sequence Spread Spectrum Base band Processor
• Manufacturer: Intersil Corporation

Data Demodulation in the CCK Modes
In this mode, the demodulator uses Complementary Code
Keying (CCK) modulation for the two highest data rates. It is
slaved to the low rate processor which it depends on for
acquisition of initial timing and phase tracking information.
The low rate section acquires the signal, locks up symbol
and carrier tracking loops, and determines the data rate to
be used for the MPDU data.
The demodulator for the CCK modes takes over when the
preamble and header have been acquired and processed.
On the last bit of the header, the phase of the signal is
captured and used as a phase reference for the high rate
differential demodulator.
The signal from the A/D converters is carrier frequency and
phase corrected by a DESPIN stage. This removes the
frequency offset and aligns the I and Q Channels properly for
the correlators. The sample rate is decimated to 11MSPS for
the correlators after the DESPIN since the data is now
synchronous in time.
The demodulator knows the symbol timing, so the
correlation is batch processed over each symbol. The
correlation outputs from the correlator are compared to each
other in a biggest picker and the chosen one determines 6
bits of the symbol. The QPSK phase of the chosen one
determines two more bits for a total of 8 bits per symbol. Six
bits come from which of the 64 correlators had the largest
output and the last two are determined from the QPSK
differential demod of that output. In the 5.5Mbps mode, only
4 of the correlator outputs are monitored. This demodulates
2 bits for which of 4 correlators had the largest output and 2
more for the QPSK demodulation of that output for a total of
4 bits per symbol.
Tracking
Carrier tracking is performed on the de-rotated signal
samples from the complex multiplier in a four phase Costas
loop. This forms the error term that is integrated in the lead/lag
filter for the NCO, closing the loop. Tracking is only measured
when there is a chip transition. Note that this tracking is
dependent on a positive SNR in the chip rate bandwidth.
The symbol clock is tracked by a sample interpolator that
can adjust the sample timing forwards and backwards by 72
increments of 1/8th chip. This approach means that the
HFA3861A can only track an offset in timing for a finite
interval before the limits of the interpolator are reached.
Thus, continuous demodulation is not possible.
19
HFA3861A
Demodulator Performance
This section indicates the typical performance measures for
a radio design. The performance data below should be used
as a guide. In general, the actual performance depends on
the application, interference environment, RF/IF
implementation and radio component selection.
Overall Eb/N0 Versus BER Performance
The PRISM chip set has been designed to be robust and
energy efficient in packet mode communications. The
demodulator uses coherent processing for data
demodulation. The figures below show the performance of
the baseband processor when used in conjunction with the
HFA3783 IF and the PRISM recommended IF filters. Off the
shelf test equipment are used for the RF processing. The
curves should be used as a guide to assess performance in
a complete implementation.
Factors for carrier phase noise, multipath, and other
degradations will need to be considered on an
implementation by implementation basis in order to predict
the overall performance of each individual system.
Figure 14 shows the curves for theoretical DBPSK/DQPSK
demodulation with coherent demodulation and
descrambling as well as the PRISM performance measured
for DBPSK and DQPSK. The theoretical performance for
DBPSK and DQPSK are the same as shown on the
diagram. Figure 15 shows the theoretical and actual
performance of the CCK modes. The losses in both figures
include RF and IF radio losses; they do not reflect the
HFA3861A losses alone. The HFA3861A baseband
processing losses from theoretical are, by themselves, a
small percentage of the overall loss.
The PRISM demodulator performs with an implementation
loss of less than 3dB from theoretical in a AWGN
environment with low phase noise local oscillators. For the
1 and 2Mbps modes, the observed errors occurred in
groups of 4 and 6 errors. This is because of the error
extension properties of differential decoding and
descrambling. For the 5.5 and 11Mbps modes, the errors
occur in symbols of 4 or 8 bits each and are further
extended by the descrambling. Therefore the error patterns
are less well defined.