STPCI01 STMicroelectronics, STPCI01 Datasheet - Page 13

• Manufacturer Part Number: STPCI01
• Description: STPC INDUSTRIAL - PC COMPATIBLE EMBEDED MICROPROC
• Manufacturer: STMicroelectronics

Table 2-2. Definition of Signal Pins
V
BASIC CLOCKS AND RESETS
SYSRSTI#*
SYSRSTO#*
XTALI
XTALO
PCI_CLKI*
PCI_CLKO
ISA_CLK, ISA_CLK2X
CLK14M
HCLK*
DEV_CLK*
GCLK2X
DCLK
MEMORY INTERFACE
MA[11:0]
RAS#[3:0]
CAS#[7:0]
MWE#
MD[63:0]
LOCAL BUS INTERFACE (COMBINED WITH ISA BUS )
PA[21:0]*
PD[15:0]*
PRDY#*
PWR#[1:0]*
PRD#[1:0]*
FCS#[1:0]*, IOCS#[3:0]*
ISA BUS INTERFACE (COMBINED WITH LOCAL BUS, PARALLEL PORT, SERIAL INTERFACE)
LA[23:17]*
SA[19:0]*
SD[15:0]*
IOCHRDY*
ALE*
BHE#*
MEMR#*, MEMW#*
SMEMR#*, SMEMW#*
IOR#*, IOW#*
MASTER#*
MCS16#*, IOCS16#*
REF#*
AEN*
IOCHCK#*
RTCRW#*
RTCDS#*
RTCAS#*
DD
_xxx_PLL
Signal Name
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
Power Supply for PLL Clocks
System Reset / Power good
Reset Output to System
14.3 MHz Crystal Input
14.3 MHz Crystal Output
33 MHz PCI/CardBus Input Clock
33 MHz PCI/CardBus Output Clock
ISA Clock x1 and x2 (also Multiplexer Select Line For IPC)
ISA bus synchronisation clock
33 / 66 MHz Host Clock (Test)
24 MHz Peripheral Clock
80 MHz Graphics Clock
135 MHz Dot Clock
Memory Address
Row Address Strobe
Column Address Strobe
Write Enable
Memory Data
Address Bus [21:0]
Data Bus [15:0]
Ready
Memory and I/O Write signals
Memory and I/O Read signals
Flash Memory and I/O Chip Select
Unlatched Address
Latched Address
Data Bus
I/O Channel Ready
Address Latch Enable
System Bus High Enable
Memory Read & Write
System Memory Read and Write
I/O Read and Write
Add On Card Owns Bus
Memory Chip Select 16, I/O Chip Select 16
Refresh Cycle
Address Enable
I/O Channel Check (ISA)
RTC Read / Write#
RTC Data Strobe
RTC Address Strobe
Issue 2.4 - February 11, 2002
Description
PIN DESCRIPTION
Qty
12
64
22
16
20
16
1
1
1
1
1
1
2
1
1
1
1
1
4
8
1
1
2
2
6
7
1
1
1
2
2
2
1
2
1
1
1
1
1
1
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