TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 546

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDLDDLY
(0290H)
LCDCTL1
(0286H)
LLDP=0
LLDP=1
Note: The delay time for the LLOAD signal is controlled based on LCDLDDLY<PDT>=1. Therefore, even if the delay
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
inserted in the LLOAD signal.
As shown in the diagram below, delay time of 0 to 127 pulses of the LCP0 clock can be
Delay time = <LDD6:0>
Signal Name
LCP0 signal
LLVSYNC signal
LHSYNC signal
(Internal reference signal)
LLOAD signal
Delay control
time is set to”0” with LCDLDDLY<PDT>=0, the LLOAD signal is output with a delay of one LCP0 clock. Be
careful about this point.
<LLDP>.
The phase of the LLOAD signal can be inverted by the setting of LCDCTL1
(Enable width control)
Data output
0: Sync with
1: 1 clock
LCP0
phase
0: Rising
1: Falling
timing
LLOAD
later than
LLOAD
LLOAD period
LCP0P
PDT
R/W
7
0
7
1
LHSYNC
phase
0: Rising
1: Falling
LDD6
LHSP
6
0
6
0
LCD Control 1 Register
LLOAD Delay Register
R/W
(Phase control)
92CF26A-544
LVSYNC
phase
0: Rising
1: Falling
LDD5
5
0
LVSP
5
1
LLOAD signal
LLOAD
phase
0: Rising
1: Falling
LDD4
4
LLDP
0
LLOAD delay (bits 6-0)
4
0
LDD3
W
3
0
3
LDD2
2
0
2
LVSYNC
enable time control
00: 1 clock of LHSYNC
01: 2 clocks of LHSYNC
10: 3 clocks of LHSYNC
11: Reserved
LDD1
LVSW1
1
0
1
0
TMP92CF26A
R/W
2009-06-25
LDD0
LVSW0
0
0
0
0