TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 207

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
000000H
On-chip I/O and
on-chip RAM
Figure 3.9.2 Recommended Memory Map for the Maximum Expansion (Physical address)
Note: In case of connecting SDRAM to the Y-area, the maximum expanded memory size is 64MB (2MB×32).
92CF26A
512 MB × 2 = 1024 MB
CSXA to CSXB ,
EA24 to EA28
LOCAL-X
CSXA
CSXB
Bank 511
Bank 255
Bank256
Bank 0
LOCAL-Y
SDCS or
92CF26A-205
64 MB (Note)
128 MB or
Bank 0
Bank 63
CS
1
CSZB
CSZA
CSZC
Bank 255
Bank 127
Bank 383
Bank128
Bank 256
Bank 0
512 MB × 4 = 2048 MB
LOCAL-Z
CSZA to CSZD ,
EA24 to EA28
CSZD
Bank 384
Bank 511
TMP92CF26A
2009-06-25

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