MAX9152 Maxim, MAX9152 Datasheet - Page 6

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MAX9152

Manufacturer Part Number
MAX9152
Description
he MAX9152 2 x 2 crosspoint switch is designed for applications requiring high speed, low power, and low-noise signal distribution
Manufacturer
Maxim
Datasheet

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800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint Switch
The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled impedance medium as defined by the ANSI
TIA/EIA-644 and IEEE 1596.3 standards. LVDS uses a
lower voltage swing than other common communication
standards, achieving higher data rates with reduced
power consumption while reducing EMI emissions and
system susceptibility to noise.
The MAX9152 is an 800Mbps 2 x 2 crosspoint switch
designed for high-speed, low-power point-to-point and
multidrop interfaces. The device accepts LVDS or dif-
ferential LVPECL signals and routes them to outputs
depending on the selected mode of operation.
A differential input with a magnitude of 0.1V to V
single-ended voltage levels at or within the MAX9152's
V
with a magnitude of at least 0.15V with single-ended volt-
age levels at or within the MAX9152's V
required to meet the AC specifications.
In the 1:2 splitter mode, the outputs repeat the selected
input. This is useful for distributing a signal or creating
a copy for use in protection switching. In the repeater
6
CC
_______________________________________________________________________________________
10, 11
13, 14
15, 16
and ground switches the output. A differential input
PIN
1, 2
3, 4
6, 7
12
5
8
9
SEL1, SEL0
IN0+, IN0-
IN1+, IN1-
EN1, EN0
NC/RSEL
OUT1-,
OUT1+
OUT0-,
OUT0+
NAME
GND
V
NC
CC
Detailed Description
LVCMOS/LVTTL Logic Inputs. Allow the switch to be configured as a mux, repeater, or splitter.
LVDS/LVPECL Differential Input 0
Power-Supply Input. Bypass V
LVDS/LVPECL Differential Input 1
Logic Input. Selects differential output resistance. Set NC/RSEL to open or low when R
set to high when R
No Connect
LVDS Differential Output 1
Ground
LVDS Differential Output 0
LVCMOS/LVTTL Logic Inputs. Enables or disables the outputs. Setting EN0 or EN1 high
enables the corresponding output, OUT0 or OUT1. Setting EN0 or EN1 low puts the
corresponding output into high impedance (differential output resistance is also high
impedance).
CC
and ground is
L
CC
= 100Ω.
with
CC
mode, the device operates as a two-channel buffer.
Repeating restores signal amplitude, allowing isolation
of media segments or longer media drive. The device is
a crosspoint switch where any input can be connected
to any output or outputs. In 2:1 mux mode, primary and
backup signals can be selected to provide a protec-
tion-switched, fault-tolerant application.
to GND with 0.1µF and 0.001µF ceramic capacitors.
Figure 1. Test Circuit for V
IN_+
IN_-
V
ID
= (V
IN_+
FUNCTION
) - (V
IN_-
1/2 MAX9152
)
ENABLED
∆V
∆V
V
V
OD
OD
OS
OD
OD
* AND V
= V
= V
AND V
and V
OUT_+
OUT_-
OS
OD
OS
R
R
- V
- V
OS
L
L
Pin Description
/2
/2
ARE MEASURED WITH V
OS
* ARE MEASURED WITH V
OS
OD
*
*
V
OS
L
ID
= 75Ω,
ID
= +100mV.
V
OD
= -100mV.

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