73S8023C Maxim, 73S8023C Datasheet - Page 13

• Manufacturer Part Number: 73S8023C
• Description: The 73S8023C is a single smart card interface IC, compliant to the electrical requirements of ISO 7816-3, EMV 4
• Manufacturer: Maxim

DS_8023C_019
The following steps list the activation sequence and the timing of the card control signals when the
system controller pulls the CMDVCC low while the RSTIN is high:
1. CMDVCC is set low.
2. Next, the internal V
3. Due to the fall of RSTIN at t
4. CLK is applied to the card at the end of t
5. RST is to be a copy of RSTIN after t
Rev. 1.5
CMDVCC
voltage V
system controller, and the power V
won’t set RST high until 42000 clock cycles after the start of CLK.
RSTIN
VCC
t
t
t
t
RST
CLK
1
2
3
4
Figure 5: Asynchronous Activation Sequence – RSTIN Low When CMDVCC Goes Low
IO
≥ 0.5 µs, CLK starts
= 0.510 ms (timing by 1.5 MHz internal Oscillator)
= 1.5 µs, I/O goes to reception state
≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
CMDVCC
RSTIN
VCC
RST
CLK
IO
CC
t
t
t
t
to the card becomes valid during this time. If not, OFF goes low to report a fault to the
1
2
3
4
Figure 6: Asynchronous Activation Sequence – Timing Diagram #2
= 0.510 ms (timing by 1.5MHz internal Oscillator)
= 1.5µs, I/O goes to reception state
= > 0.5µs, CLK active
≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
CC
control circuit checks the presence of V
t
1
2
, turn I/O (AUX1, AUX2) to reception mode.
t
1
CC
4
. RSTIN may be set high before t
to the card is turned off.
3
after I/O is in reception mode.
t
2
t
2
t
3
t
3
CC
at t
t
4
4
, however the sequencer
t
4
1
. In normal operation, the
73S8023C Data Sheet
13