ST72321R6-Auto STMicroelectronics, ST72321R6-Auto Datasheet - Page 47

• Manufacturer Part Number: ST72321R6-Auto
• Description: 8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321R6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
6.6.5
System Integrity (SI) Control/Status register (SICSR)
Table 13.
Table 14.
SICSR
Bit
3:1
7
6
5
4
0
AVDS
RW
7
WDGRF
LVDRF
AVDIE
Name
AVDS
AVDF
-
SICSR description
Reset source flags
AVDIE
Voltage Detection selection
Voltage Detector interrupt enable
Voltage Detector flag
LVD reset flag
Reserved, must be kept cleared.
Watchdog reset flag
RW
6
This bit is set and cleared by software. Voltage Detection is available only if the
LVD is enabled by option byte.
0: Voltage detection on V
1: Voltage detection on EVD pin
This bit is set and cleared by software. It enables an interrupt to be generated
when the AVDF flag changes (toggles). The pending interrupt information is
automatically cleared when software enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an
interrupt request is generated when the AVDF bit changes value. Refer to
Figure 15
details.
0: V
1: V
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (writing zero). See
source flags
LVDRF bit value is undefined.
This bit indicates that the last Reset was generated by the Watchdog peripheral. It
is set by hardware (watchdog reset) and cleared by software (writing zero) or an
LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF flag information, the flag description is given in
Table
External RESET pin
DD
DD
Reset sources
14.
Watchdog
or V
or V
AVDF
LVD
and to
RW
EVD
EVD
5
for more details. When the LVD is disabled by OPTION BYTE, the
Doc ID 13829 Rev 1
over V
under V
Monitoring the VDD main supply on page 44
LVDRF
IT+(AVD)
RW
IT-(AVD)
4
DD
supply
threshold
threshold
Function
3
Supply, reset and clock management
Reserved
LVDRF
2
-
Reset value:
0
0
1
for additional
1
000x 000x (00h)
Table 14: Reset
WDGRF
X
0
1
WDGRF
RW
0
47/243