ST72321R6-Auto STMicroelectronics, ST72321R6-Auto Datasheet - Page 35

• Manufacturer Part Number: ST72321R6-Auto
• Description: 8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321R6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
5.3.5
Table 7.
Table 8.
Table 9.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
given by the corresponding bits in the interrupt software priority registers (ISPRx). They can
be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP
instructions.
See
Stack pointer (SP) register
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
SP
Bit Name
Bit Name
7
1
0
3
15
5
0
Chapter 7: Interrupts on page 49
I1
I0
14
C
Z
0
Zero
Carry/borrow
Interrupt Software Priority 1
Interrupt Software Priority 0
Arithmetic management bits
Interrupt management bits
Interrupt software priority selection
13
0
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the “bit test and branch”, shift and rotate
instructions.
The combination of the I1 and I0 bits gives the current interrupt software priority.
The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt software priority
12
0
11
0
Doc ID 13829 Rev 1
10
0
9
0
for more details.
8
1
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
(continued)
RW
Function
Function
7
RW
6
RW
Level
High
Central processing unit (CPU)
Low
5
RW
4
RW
3
I1
Reset value: 01 FFh
1
0
0
1
RW
2
RW
1
I0
0
1
0
1
35/243
RW
0