STR910FAZ32 STMicroelectronics, STR910FAZ32 Datasheet - Page 63

• Manufacturer Part Number: STR910FAZ32
• Description: 32-bit MCU
• Manufacturer: STMicroelectronics

Specifications of STR910FAZ32

• Arm966e-s Risc Core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)

STR91xFAxxx
7.5.1
LVD delay timing
Case 1: When V
(introduced by the VDD rising edge), a new ~10 ms delay starts before the release of
RESET_OUTn. See
Figure 12. LVD reset delay case 1
Case 2: When V
(introduced by the VDD rising edge), RESET_OUTn will be released immediately at the end
of the delay. No new delay is introduced in this case. See
Figure 13. LVD reset delay case 2
Case 3: When V
RESET_OUTn will be released at the end of a ~10 ms delay. See
Figure 14. LVD reset delay case 3
V
V
RESET_OUTn (blue)
V
V
V
V
RESET_OUTn (blue)
RESET_OUTn (blue)
DD
DDQ
DD
DDQ
DD
DDQ
(green)
(green)
(green)
(red)
(red)
(red)
V
DDQ
DDQ
DD
V
DD_LVD+
DD_LVD+
reaches the V
Figure 12.
reaches the V
reaches the V
V
V
~10 ms delay
DDQ_LVD+
DDQ_LVD+
~10 ms delay
Doc ID 13495 Rev 6
DD_LVD+
DDQ_LVD+
DDQ_LVD+
V
DD_LVD+
threshold after the V
threshold after the first ~10 ms delay
threshold before the first ~10 ms delay
~10 ms delay
Figure 13.
V
DDQ_LVD+
DDQ
Electrical characteristics
Figure 14
rising edge,
~10 ms delay
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