ST72324BK2 STMicroelectronics, ST72324BK2 Datasheet - Page 58

• Manufacturer Part Number: ST72324BK2
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BK2

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

I/O ports
9
9.1
9.2
9.2.1
Note:
58/193
1
2
3
I/O ports
Introduction
The I/O ports offer different functional modes:
●
and for specific pins:
●
●
An I/O port contains up to 8 pins. Each pin can be programmed independently as digital
input (with or without interrupt generation) or digital output.
Functional description
Each port has two main registers:
●
●
and one optional register:
●
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR
registers: bit X corresponding to pin X of the port. The same correspondence is used for the
DR register.
The following description takes into account the OR register, (for specific ports which do not
provide this register refer to
I/O block diagram is shown in
Input modes
The input configuration is selected by clearing the corresponding DDR register bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can be selected by software through the OR register.
Writing the DR register modifies the latch value but does not affect the pin status.
When switching from input to output mode, the DR register has to be written first to drive the
correct level on the pin as soon as the port is configured as an output.
Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this
might corrupt the DR content for I/Os configured as input.
transfer of data through digital inputs and outputs,
external interrupt generation,
alternate signal input/output for the on-chip peripherals.
Data Register (DR)
Data Direction Register (DDR)
Option Register (OR)
Section 9.3: I/O port implementation on page
Figure 30.
62). The generic
ST72324Bxx