STM8L101K3 STMicroelectronics, STM8L101K3 Datasheet - Page 56
STM8L101K3
Manufacturer Part Number
STM8L101K3
Description
Ultra Low Power MCUs, STM8L
Manufacturer
STMicroelectronics
Datasheet
1.STM8L101G2.pdf
(81 pages)
Specifications of STM8L101K3
Low Power Consumption (halt
0.3 μA, Active-halt
Temp. Range
-40 to 85 °C and 125 °C
Three Low Power Modes
Wait, Active-halt, Halt
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Electrical parameters
56/81
Figure 31. Typical NRST pull-up current I
The reset network shown in
must ensure that the level on the NRST pin can go below the V
Table
sensitive applications, the capacity of the external reset capacitor can be reduced to limit the
charge/discharge current. If the NRST signal is used to reset the external circuitry, the user
must pay attention to the charge/discharge time of the external capacitor to meet the reset
timing conditions of the external devices. The minimum recommended capacity is 10 nF
Figure 32. Recommended NRST pin configuration
EXTERNAL
CIRCUIT
30. Otherwise the reset is not taken into account internally. For power consumption-
RESET
120
100
80
60
40
20
0
1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85
0.1 F
Figure 32
-40°C
25°C
85°C
125°C
Doc ID 15275 Rev 11
RSTIN
protects the device against parasitic resets. The user
V
DD
V
DD
R
[V]
PU
pu
vs. V
3
DD
3.15 3.3 3.45 3.6
Filter
ai17006
IL
INTERNAL RESET
max. level specified in
STM8L
STM8L101xx