BUK9618-55A NXP Semiconductors, BUK9618-55A Datasheet

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology

BUK9618-55A

Manufacturer Part Number
BUK9618-55A
Description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology
Manufacturer
NXP Semiconductors
Datasheet

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BUK9618-55A
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BUK9618-55A
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1. Product profile
1.1 General description
1.2 Features and benefits
1.3 Applications
1.4 Quick reference data
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
Table 1.
Symbol
V
P
Static characteristics
R
I
D
DS
tot
DSon
BUK9618-55A
N-channel TrenchMOS logic level FET
Rev. 02 — 16 February 2011
AEC Q101 compliant
Low conduction losses due to low
on-state resistance
12 V and 24 V loads
Automotive and general purpose
power switching
Quick reference data
Parameter
drain-source
voltage
drain current
total power
dissipation
drain-source
on-state
resistance
Conditions
T
V
see
T
V
T
V
T
V
T
see
j
mb
j
j
j
GS
GS
GS
GS
≥ 25 °C; T
= 25 °C
= 25 °C
= 25 °C; see
Figure
Figure 12
= 25 °C; see
= 5 V; T
= 10 V; I
= 4.5 V; I
= 5 V; I
1; see
D
mb
j
D
≤ 175 °C
= 25 A;
D
= 25 A;
= 25 °C;
= 25 A;
Figure
Figure 2
Figure 3
11;
Suitable for logic level gate drive
sources
Suitable for thermally demanding
environments due to 175 °C rating
Motors, lamps and solenoids
Min
-
-
-
-
-
-
Product data sheet
Typ
-
-
-
12
-
14
Max Unit
55
61
136
16
19
18
V
A
W
mΩ
mΩ
mΩ

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BUK9618-55A Summary of contents

Page 1

... BUK9618-55A N-channel TrenchMOS logic level FET Rev. 02 — 16 February 2011 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET plastic package using TrenchMOS technology. This product has been designed and qualified to the appropriate AEC standard for use in automotive critical applications. ...

Page 2

... Simplified outline SOT404 (D2PAK) Description plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 February 2011 BUK9618-55A N-channel TrenchMOS logic level FET Min ≤ sup = °C; ...

Page 3

... °C; unclamped GS j(init) 03nf37 120 P der (%) 150 175 200 T (°C) mb Fig 2. All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 February 2011 BUK9618-55A N-channel TrenchMOS logic level FET Min - - -15 Figure 1; - Figure 1 - ≤ 10 µ -55 - ° Ω; ...

Page 4

... Figure 4 minimum footprint; mounted on a printed-circuit board −5 −4 − All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 February 2011 BUK9618-55A N-channel TrenchMOS logic level FET 03ne48 μs 100 μ 100 (V) DS ...

Page 5

... °C j from source lead to source bond pad °C j All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 February 2011 BUK9618-55A N-channel TrenchMOS logic level FET Min Typ Max ...

Page 6

... 2 (V) DS Fig 6. 03aa36 max (V) GS Fig 8. All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 February 2011 BUK9618-55A N-channel TrenchMOS logic level FET Min Typ - 0. ° 101 20 DSon Drain-source on-state resistance as a function of gate-source voltage ...

Page 7

... V (V) GS Fig 10. Gate-source threshold voltage as a function of 03ne46 5 4 150 200 I (A) D Fig 12. Normalized drain-source on-state resistance All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 February 2011 BUK9618-55A N-channel TrenchMOS logic level FET 2.5 V GS(th) (V) 2 max 1.5 typ min 1 0.5 0 -60 0 ...

Page 8

... 175 ° 0.2 0.4 0.6 0.8 All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 February 2011 BUK9618-55A N-channel TrenchMOS logic level FET C iss C oss C rss 0 −2 − function of drain-source voltage; typical values 03ne40 = 25 °C ...

Page 9

... max. 1.60 10.30 2.90 15.80 11 2.54 1.20 9.70 2.10 14.80 REFERENCES JEDEC JEITA All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 February 2011 BUK9618-55A N-channel TrenchMOS logic level FET mounting base 2.60 2.20 EUROPEAN ISSUE DATE PROJECTION 05-02-11 06-03-16 © NXP B.V. 2011. All rights reserved. SOT404 ...

Page 10

... The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Type number BUK9618-55A separated from data sheet BUK9518_9618_55A v.1. BUK9518_9618_55A v.1 20010827 BUK9618-55A Product data sheet ...

Page 11

... In case an individual All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 February 2011 BUK9618-55A N-channel TrenchMOS logic level FET © NXP B.V. 2011. All rights reserved ...

Page 12

... TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 February 2011 BUK9618-55A N-channel TrenchMOS logic level FET Trademarks © NXP B.V. 2011. All rights reserved ...

Page 13

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 16 February 2011 Document identifier: BUK9618-55A ...

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