LPC11C12FBD48 NXP Semiconductors, LPC11C12FBD48 Datasheet - Page 16

The LPC11C12FBD48 is an ARM Cortex-M0 microcontroller designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit arch

LPC11C12FBD48

Manufacturer Part Number
LPC11C12FBD48
Description
The LPC11C12FBD48 is an ARM Cortex-M0 microcontroller designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit arch
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
LPC11CX2_CX4
Product data sheet
Fig 4.
LPC11Cx2/Cx4 memory map
0.5 GB
0 GB
4 GB
1 GB
7.5.1 Features
7.5 Nested Vectored Interrupt Controller (NVIC)
16 kB on-chip flash (LPC11Cx2)
32 kB on-chip flash (LPC11Cx4)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
private peripheral bus
LPC11Cx2/Cx4
AHB peripherals
16 kB boot ROM
APB peripherals
8 kB SRAM
Controls system exceptions and peripheral interrupts.
In the LPC11Cx2/Cx4, the NVIC supports 32 vectored interrupts including 13 inputs to
the start logic from individual GPIO pins.
reserved
reserved
reserved
reserved
reserved
reserved
reserved
All information provided in this document is subject to legal disclaimers.
0xFFFF FFFF
0xE010 0000
0xE000 0000
0x5020 0000
0x5000 0000
0x4008 0000
0x4000 0000
0x2000 0000
0x1FFF 4000
0x1FFF 0000
0x1000 2000
0x1000 0000
0x0000 8000
0x0000 4000
0x0000 0000
Rev. 3 — 27 June 2011
active interrupt vectors
22
21
20
19
18
17
16
15
14
9
8
7
6
5
4
3
2
1
0
12-15
8-11
4-7
0-3
32-bit ARM Cortex-M0 microcontroller
16 - 127 reserved
32-bit counter/timer 1
32-bit counter/timer 0
16-bit counter/timer 1
16-bit counter/timer 0
AHB peripherals
APB peripherals
23 - 31 reserved
10 - 13 reserved
system control
flash controller
GPIO PIO3
GPIO PIO2
GPIO PIO1
GPIO PIO0
IOCONFIG
reserved
reserved
reserved
reserved
C_CAN
I
LPC11Cx2/Cx4
2
ADC
UART
PMU
WDT
SPI1
SPI0
0x0000 00C0
0x0000 0000
C-bus
0x4008 0000
0x4005 C000
0x4005 8000
0x4005 4000
0x4005 0000
0x4004 C000
0x4004 8000
0x4004 4000
0x4004 0000
0x4003 C000
0x4003 8000
0x4002 8000
0x4002 4000
0x4002 0000
0x4001 C000
0x4001 8000
0x4001 4000
0x4001 0000
0x4000 C000
0x4000 8000
0x4000 4000
0x4000 0000
0x5020 0000
0x5004 0000
0x5003 0000
0x5002 0000
0x5001 0000
0x5000 0000
© NXP B.V. 2011. All rights reserved.
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