ADUC824 Analog Devices, ADUC824 Datasheet - Page 47

• Manufacturer Part Number: ADUC824
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC824

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

PSMCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
POWER SUPPLY MONITOR
As its name suggests, the Power Supply Monitor, once enabled,
monitors both supplies (AVDD or DVDD) on the ADuC824. It
will indicate when any of the supply pins drop below one of
four user-selectable voltage trip points from 2.63 V to 4.63 V.
For correct operation of the Power Supply Monitor function,
AV
is controlled via the PSMCON SFR. If enabled via the IEIP2
SFR, the monitor will interrupt the core using the PSMI bit in the
DD
C
M
must be equal to or greater than 2.7 V. Monitor function
P
D
Name
CMPD
CMPA
PSMI
TPD1
TPD0
TPA1
TPA0
PSMEN
C
M
P
A
Power Supply Monitor Control Register
Description
DVDD Comparator Bit
This is a read-only bit and directly reflects the state of the DVDD comparator.
Read ‘1’ indicates the DVDD supply is above its selected trip point.
Read ‘0’ indicates the DVDD supply is below its selected trip point.
AVDD Comparator Bit
This is a read-only bit and directly reflects the state of the AVDD comparator.
Read ‘1’ indicates the AVDD supply is above its selected trip point.
Read ‘0’ indicates the AVDD supply is below its selected trip point.
Power Supply Monitor Interrupt Bit
This bit will be set high by the MicroConverter if either CMPA or CMPD are low, indicating
low analog or digital supply. The PSMI bit can be used to interrupt the processor. Once CMPD
and/or CMPA return (and remain) high, a 250 ms counter is started. When this counter times
out, the PSMI interrupt is cleared. PSMI can also be written by the user. However, if either com-
parator output is low, it is not possible for the user to clear PSMI.
DVDD Trip Point Selection Bits
These bits select the DVDD trip-point voltage as follows:
TPD1
0
0
1
1
AVDD Trip Point Selection Bits
These bits select the AVDD trip-point voltage as follows:
TPA1
0
0
1
1
Power Supply Monitor Enable Bit
Set to ‘1’ by the user to enable the Power Supply Monitor Circuit.
Cleared to ‘0’ by the user to disable the Power Supply Monitor Circuit.
DFH
DEH
No
P
S
M
Table XVIII. PSMCON SFR Bit Designations
I
TPD0
0
1
0
1
TPA0
0
1
0
1
T
P
D
1
Selected DVDD Trip Point (V)
4.63
3.08
2.93
2.63
Selected AVDD Trip Point (V)
4.63
3.08
2.93
2.63
PSMCON SFR. This bit will not be cleared until the failing
power supply has returned above the trip point for at least
250 ms. This monitor function allows the user to save working
registers to avoid possible data loss due to the low supply condi-
tion, and also ensures that normal code execution will not
resume until a safe supply level has been well established. The
supply monitor is also protected against spurious glitches trig-
gering the interrupt circuit.
T
P
D
0
T
P
A
1
T
P
A
0
ADuC824
P
S
M
E
N