ADUC824 Analog Devices, ADUC824 Datasheet - Page 22

• Manufacturer Part Number: ADUC824
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC824

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

MEMORY ORGANIZATION
As with all 8051-compatible devices, the ADuC824 has sepa-
rate address spaces for Program and Data memory as shown in
Figure 13 and Figure 14.
If the user applies power or resets the device while the EA pin is
pulled low, the part will execute code from the external program
space, otherwise the part defaults to code execution from its
internal 8 Kbyte Flash/EE program memory. This internal code
space can be downloaded via the UART serial port while the
device is in-circuit.
The data memory address space consists of internal and exter-
nal memory space. The internal memory space is divided into
four physically separate and distinct blocks, namely the lower
128 bytes of RAM, the upper 128 bytes of RAM, the 128 bytes
of special function register (SFR) area, and a 640-byte Flash/EE
Data memory. While the upper 128 bytes of RAM, and the SFR
area share the same address locations, they are accessed through
different address modes.
The lower 128 bytes of data memory can be accessed through
direct or indirect addressing, the upper 128 bytes of RAM can
be accessed through indirect addressing, and the SFR area is
accessed through direct addressing.
Also, as shown in Figure 13, the additional 640 Bytes of
Flash/EE Data Memory are available to the user and can be
accessed indirectly via a group of control registers mapped into
the Special Function Register (SFR) area. Access to the Flash/
EE Data memory is discussed in detail later as part of the Flash/
EE memory section in this data sheet.
The external data memory area can be expanded up to 16 Mbytes.
This is an enhancement of the 64 KByte external data memory
space available on standard 8051-compatible cores.
The external data memory is discussed in more detail in the
ADuC824 Hardware Design Considerations section.
ADuC824
PROGRAM
INTERNAL
FLASH/EE
MEMORY
8 KBYTE
EA = 1
FFFFH
2000H
PROGRAM MEMORY SPACE
READ ONLY
EXTERNAL
PROGRAM
MEMORY
1FFFH
0000H
SPACE
EXTERNAL
PROGRAM
MEMORY
SPACE
EA = 0
The lower 128 bytes of internal data memory are mapped as shown
in Figure 15. The lowest 32 bytes are grouped into four banks
of eight registers addressed as R0 through R7. The next 16 bytes
(128 bits), locations 20 Hex through 2 FHex above the regis-
ter banks, form a block of directly addressable bit locations at
bit addresses 00H through 7FH. The stack can be located any-
where in the internal memory address space, and the stack depth
can be expanded up to 256 bytes.
Reset initializes the stack pointer to location 07 Hex and incre-
ments it once to start from locations 08 Hex which is also the first
register (R0) of register bank 1. Thus, if one is going to use
more than one register bank, the stack pointer should be initialized
to an area of RAM not used for data storage.
BITS IN PSW
SELECTED
00H
9FH
LOWER
BANKS
UPPER
128
128
VIA
CONTROL REGISTERS
7FH
80H
FFH
00H
FLASH/EE DATA
10
11
01
INDIRECTLY
00
ACCESSED
(PAGE 159)
640 BYTES
DATA MEMORY
AND INDIRECT
MEMORY
(PAGE 0)
ADDRESSING
ADDRESSING
VIA SFR
ACCESSIBLE
ACCESSIBLE
INTERNAL
INDIRECT
SPACE
DIRECT
ONLY
BY
BY
30H
20H
18H
10H
08H
00H
DATA MEMORY SPACE
ADDRESSING
ACCESSIBLE
REGISTERS
BY DIRECT
FUNCTION
SPECIAL
READ/WRITE
ONLY
7FH
2FH
1FH
17H
0FH
07H
FFH
80H
FFFFFFH
000000H
GENERAL-PURPOSE
AREA
BIT-ADDRESSABLE
(BIT ADDRESSES)
FOUR BANKS OF EIGHT
REGISTERS
R0 R7
RESET VALUE OF
STACK POINTER
EXTERNAL
ADDRESS
MEMORY
SPACE)
SPACE
(24-BIT
DATA