AD8041 Analog Devices, AD8041 Datasheet - Page 11

• Manufacturer Part Number: AD8041
• Description: 160 MHz Rail-to-Rail Amplifier with Disable
• Manufacturer: Analog Devices

Specifications of AD8041

• Vcc-vee: 3V to 12V
• Isy Per Amplifier: 6.5mA
• Packages: SOIC,DIP
• -3db Bandwidth: 170MHz
• Slew Rate: 170V/µs
• Vos: 2mV
• Ib: 1.2µA
• # Opamps Per Pkg: 1
• Input Noise (nv/rthz): 16nV/rtHz

Overdrive Recovery
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this over-
drive condition. As shown in Figure 4, the AD8041 recovers
within 50 ns from negative overdrive and within 25 ns from
positive overdrive.
Circuit Description
The AD8041 is fabricated on Analog Devices’ proprietary
eXtra-Fast Complementary Bipolar (XFCB) process, which
enables the construction of PNP and NPN transistors with similar
f
isolated to eliminate the parasitic and latch-up problems caused
by junction isolation. These features allow the construction of
high frequency, low distortion amplifiers with low supply currents.
This design uses a differential output input stage to maximize
bandwidth and headroom (see Figure 5). The smaller signal
swings required on the first stage outputs (nodes S1P, S1N) reduce
the effect of nonlinear currents due to junction capacitances and
improve the distortion performance. With this design harmonic
distortion of better than –85 dB @ 1 MHz into 100 Ω with V
2 V p-p (Gain = +2) on a single 5 V supply is achieved.
The complementary common-emitter design of the output stage
provides excellent load drive without the need for emitter follow-
ers, thereby improving the output range of the device consider-
ably with respect to conventional op amps. High output drive
capability is provided by injecting all output stage predriver
currents directly into the bases of the output devices Q8 and
Q36. Biasing of Q8 and Q36 is accomplished by I8 and I5,
along with a common-mode feedback loop (not shown). This
circuit topology allows the AD8041 to drive 50 mA of output
current with the outputs within 0.5 V of the supply rails.
On the input side, the device can handle voltages from –0.2 V
below the negative rail to within 1.2 V of the positive rail. Exceed-
ing these values will not cause phase reversal; however, the
input ESD devices will begin to conduct if the input voltages
exceed the rails by greater than 0.5 V.
A “Nested Integrator” topology is used in the AD8041 (see
the small-signal schematic in Figure 6). The output stage can
be modeled as an ideal op amp with a single-pole response and
a unity-gain frequency set by transconductance g
REV. B
T
in the 2 GHz to 4 GHz region. The process is dielectrically
5.0V
2.5V
0V
Figure 4. Overdrive Recovery
INPUT
50mV
G = +2
V
S
= 5V
40ns
OUTPUT
m2
and
OUT
=
–11–
Capacitor C9. R1 is the output resistance of the input stage; g
is the input transconductance. C7 and C9 provide Miller com-
pensation for the overall op amp. The unity gain frequency will
occur at g
where A0 = g
The first pole in the denominator is the dominant pole of the
amplifier and occurs at about 180 Hz. This equals the input
stage output impedance R1 multiplied by the Miller-multiplied
value of C9. The second pole occurs at the unity-gain bandwidth
of the output stage, which is 250 MHz. This type of architecture
allows more open-loop gain and output drive to be obtained
than a standard two-stage architecture would allow.
Output Impedance
The low frequency open-loop output impedance of the common
emitter output stage used in this design is approximately 6.5 kΩ.
While this is significantly higher than a typical emitter follower
output stage, when connected with feedback, the output imped-
ance is reduced by the open-loop gain of the op amp. With
110 dB of open-loop gain, the output impedance is reduced
to less than 0.1 Ω. At higher frequencies, the output impedance
will rise as the open-loop gain of the op amp drops; however, the
output also becomes capacitive due to the integrator capacitors
C9 and C3. This prevents the output impedance from ever becom-
ing excessively high (see TPC 15), which can cause stability
problems when driving capacitive loads. In fact, the AD8041
has excellent cap-load drive capability for a high frequency op
amp. TPC 22 demonstrates that the AD8041exhibits a 45°
margin while driving a 20 pF direct capacitive load. In addition,
running the part at higher gains will also improve the capacitive
load drive capability of the op amp.
V
V
V
V
IN
IN
CC
EE
P
N
Q13
R15
V
C7
A2 = g
OUT
Vi
m
R2
Figure 5. AD8041 Simplified Schematic
/C9. Solving the node equations for this circuit yields:
I1
Q17
R26
=
Q2
Q4
m
m2
(
g
R5
sR
m2
Q40
R2
S1P
V
1
EE
I10
R2 R1
Q3
[
C
Q5
R39
R21
9
S1N
(
A
Q11
2
R3
I2
(Open-Loop Gain of Op Amp)
(Open-Loop Gain of Output Stage)
+
Q22
1
I3
)]
Q7
A
Q25
Q24
+
I7
0
Q51
Q21
1
R23 R27
)
×



Q39
Q27
s
Q50
Q47



Q31
g
AD8041
C
m
Q23
3
2

 +

I9
V
CC
V
1
EE



I8
C3
C9
I5
Q36
Q8
V
OUT
m