AD9751 Analog Devices, AD9751 Datasheet - Page 14

• Manufacturer Part Number: AD9751
• Manufacturer: Analog Devices

Specifications of AD9751

• Resolution (bits): 10bit
• Dac Update Rate: 300MSPS
• Dac Settling Time: 11ns
• Max Pos Supply (v): +3.6V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

AD9751
Equations 7 and 8 highlight some of the advantages of operating
the AD9751 differentially. First, the differential operation helps
cancel common-mode error sources associated with I
I
differential code-dependent current and subsequent voltage, V
is twice the value of the single-ended voltage output (i.e., V
or V
Note that the gain drift temperature performance for a single-
ended (V
AD9751 can be enhanced by selecting temperature tracking
resistors for R
ship, as shown in Equation 8.
ANALOG OUTPUTS
The AD9751 produces two complementary current outputs,
I
differential operation. I
complementary single-ended voltage outputs, V
via a load resistor, R
in the DAC Transfer Function section. The differential voltage,
V
to a single-ended voltage via a transformer or differential ampli-
fier configuration. The ac performance of the AD9751 is optimum
and is specified using a differential transformer-coupled output in
which the voltage swing at I
If a single-ended unipolar output is desirable, I
selected as the output, with I
The distortion and noise performance of the AD9751 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both I
significantly reduced by the common-mode rejection of a trans-
former or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more signifi-
cant as the frequency content of the reconstructed waveform
increases. This is due to the first order cancellation of various
dynamic common-mode distortion mechanisms, digital feed-
through, and noise.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the recon-
structed signal power to the load (i.e., assuming no source
termination). Since the output currents of I
complementary, they become additive when processed differen-
tially. A properly selected transformer will allow the AD9751 to
provide the required power and voltage levels to different loads.
Refer to Applying the AD9751 section for examples of various
output configurations.
The output impedance of I
equivalent parallel combination of the PMOS switches associ-
ated with the current sources and is typically 100 kΩ in parallel
with 5 pF. It is also slightly dependent on the output voltage
(i.e., V
As a result, maintaining I
via an I-V op amp configuration will result in the optimum dc
linearity. Note that the INL/DNL specifications for the AD9751
are measured with I
via an op amp.
I
compliance range that must be adhered to in order to achieve
OUTB
OUTA
OUTA
DIFF
OUTB
, existing between V
and I
such as noise, distortion, and dc offsets. Second, the
and I
OUTA
), thus providing twice the signal power to the load.
OUTA
OUTB
OUTB
and V
LOAD
and V
, that may be configured for single-ended or
also have a negative and positive voltage
OUTB
and R
OUTA
LOAD
OUTB
OUTA
) due to the nature of a PMOS device.
, as described by Equations 5 through 8
and I
) or differential output (V
OUTA
SET
OUTA
OUTA
OUTA
OUTB
due to their ratiometric relation-
and I
OUTB
and/or I
and V
and I
and I
grounded.
OUTB
maintained at virtual ground
OUTB
OUTB
OUTB
OUTA
OUTB
can be converted into
can also be converted
is limited to ± 0.5 V.
is determined by the
OUTA
and I
at a virtual ground
OUTA
OUTA
OUTB
and I
DIFF
should be
OUTA
and V
) of the
OUTB
can be
and
OUTB
OUTA
are
DIFF
,
,
–14–
optimum performance. The negative output compliance range
of –1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break-
down of the output stage and affect the reliability of the AD9751.
The positive output compliance range is slightly dependent on
the full-scale output current, I
nominal 1.25 V for an I
= 2 mA. The optimum distortion performance for a single-
ended or differential output is achieved when the maximum
full-scale signal at I
Applications requiring the AD9751’s output (i.e., V
V
accordingly. Operation beyond this compliance range will adversely
affect the AD9751’s linearity performance and subsequently
degrade its distortion performance.
DIGITAL INPUTS
The AD9751’s digital input consists of two channels of 10 data
input pins each and a pair of differential clock input pins. The
10-bit parallel data inputs follow standard straight binary coding
where DB9 is the most significant bit (MSB) and DB0 is the
least significant bit (LSB). I
current when all data bits are at Logic 1. I
complementary output with the full-scale current split between
the two outputs as a function of the input code.
The digital interface is implemented using an edge-triggered
master slave latch. With the PLL active or disabled, the DAC
output is updated twice for every input latch rising edge, as
shown in Figures 7 and 11. The AD9751 is designed to support
an input data rate as high as 150 MSPS, giving a DAC output
update rate of 300 MSPS. The setup-and-hold times can also be
varied within the clock cycle as long as the specified minimum
times are met. Best performance is typically achieved when the
input data transitions on the falling edge of a 50% duty cycle clock.
The digital inputs are CMOS compatible with logic thresholds,
VTHRESHOLD, set to approximately half the digital positive
supply (DVDD) or
The internal digital circuitry of the AD9751 is capable of oper-
ating over a digital supply range of 3.0 V to 3.6 V. As a result,
the digital inputs can also accommodate TTL levels when DVDD
is set to accommodate the maximum high level voltage of the
TTL drivers V
ensures proper compatibility with most TTL logic families.
Figure 14 shows the equivalent digital input circuit for the data
and clock inputs.
The AD9751 features a flexible differential clock input operating
from separate supplies (i.e., CLKVDD, CLKCOM) to achieve
optimum jitter performance. The two clock inputs, CLK+ and
OUTB
) to extend its output compliance range should size R
Figure 14. Equivalent Digital Input
VTHRESHOLD
OH
(max). A DVDD of 3.0 V to 3.6 V typically
DIGITAL
INPUT
OUTA
OUTFS
and I
OUTA
= 20 mA to 1.00 V for an I
OUTFS
OUTB
=
produces a full-scale output
DVDD
. It degrades slightly from its
does not exceed 1.0 V.
2
DVDD
(
OUTB
±
20%
produces a
)
OUTA
REV. C
OUTFS
and/or
LOAD