AD5611 Analog Devices, AD5611 Datasheet - Page 17

• Manufacturer Part Number: AD5611
• Description: 2.7 V to 5.5 V,
• Manufacturer: Analog Devices

Specifications of AD5611

• Resolution (bits): 10bit
• Dac Update Rate: 1.7MSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

Data Sheet
AD5601/AD5611/AD5621 to Blackfin® ADSP-BF53x
Interface
Figure 48 shows a serial interface between the AD5601/AD5611/
AD5621 and the Blackfin ADSP-BF53x microprocessor. The
ADSP-BF53x processor family incorporates two dual-channel
synchronous serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5601/AD5611/AD5621, the setup for the interface is as
follows: DT0PRI drives the SDIN pin of the AD5601/AD5611/
AD5621, while TSCLK0 drives the SCLK of the part. The SYNC
is driven from TFS0.
AD5601/AD5611/AD5621 to 80C51/80L51 Interface
Figure 49 shows a serial interface between the AD5601/
AD5611/AD5621 and the 80C51/80L51 microcontroller. The
setup for the interface is as follows: TxD of the 80C51/80L51
drives SCLK of the AD5601/AD5611/AD5621, while RxD
drives the serial data line of the part. The SYNC signal is again
derived from a bit programmable pin on the port. In this case,
Port Line P3.3 is used. When data is to be transmitted to the
AD5601/AD5611/AD5621, P3.3 is taken low. The 80C51/80L51
transmit data only in 8-bit bytes; therefore, only eight falling
clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left low after the first eight bits are transmitted,
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 48. AD5601/AD5611/AD5621 to Blackfin ADSP-BF53x Interface
ADSP-BF53x*
TSCLK0
DT0PRI
TFS0
AD5601/AD5611/
AD5621*
SDIN
SCLK
SYNC
Rev. F | Page 17 of 24
and a second write cycle is initiated to transmit the second byte
of data. P3.3 is taken high following the completion of this
cycle. The 80C51/80L51 output the serial data LSB first. The
AD5601/AD5611/AD5621 require data with the MSB as the
first bit received. The 80C51/80L51 transmit routine should
take this into account.
AD5601/AD5611/AD5621 to MICROWIRE Interface
Figure 50 shows an interface between the AD5601/AD5611/
AD5621 and any MICROWIRE-compatible device. Serial data
is shifted out on the falling edge of the serial clock and is
clocked into the AD5601/AD5611/AD5621 on the rising edge
of the SK.
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 49. AD5601/AD5611/AD5621 to 80C51/80L51 Interface
Figure 50. AD5601/AD5611/AD5621 to MICROWIRE Interface
80C51/80L51*
MICROWIRE*
P3.3
RxD
TxD
SO
CS
SK
AD5601/AD5611/AD5621
AD5601/AD5611/
AD5621*
SYNC
SCLK
SDIN
AD5601/AD5611/
AD5621*
SYNC
SCLK
SDIN