AD9860 Analog Devices, AD9860 Datasheet - Page 18

• Manufacturer Part Number: AD9860
• Description: 10-/12-Bit Mixed Signal Front-End (MxFE®) Processor for Broadband Communications
• Manufacturer: Analog Devices

Specifications of AD9860

• Resolution (bits): 10bit
• # Chan: 2
• Sample Rate: 64MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,2 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

AD9860/AD9862
Read Operation
The read back of registers is a single data byte operation. The
readback can be configured to use three pins or four pins and can
be formatted as MSB first or LSB first. The instruction header
is written to the device either MSB or LSB first (depending on
the mode) followed by the 8-bit output data (appropriately MSB
or LSB justified). By default, the output data is sent to the dedicated
output pin (SDO). 3-wire operation can be configured by set-
ting the SDIO BiDir register. In 3-wire mode, the SDIO pin
will become an output pin after receiving the 8-bit instruction
header with a read back request.
Figure 2a shows an MSB first, 4-pin SPI read; Figure 2b shows an
MSB first, 3-pin read; and Figure 2c shows an LSB first, 4-pin read.
SYSTEM BLOCK DESCRIPTION
The AD9860/AD9862 integrates transmit and receive paths with
digital signal processing blocks and auxiliary features. The auxiliary
Figure 2. SPI Read Examples a. (top) 4-Wire Interface, MSB first; b. (middle) 3-Wire Interface, MSB first;
c. (bottom) 4-Wire Interface, LSB first
SCLK
SCLK
SCLK
SDIO
SDIO
SDIO
SDO
SDO
SEN
SEN
SEN
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t
t
t
S
S
S
R/nW 2/n1
R/nW
A0
INSTRUCTION HEADER (REGISTER N)
2/n1
A1
t
t
t
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DS
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DS
DS
INSTRUCTION HEADER
INSTRUCTION HEADER
A5
A5
A2
t
t
t
DH
DH
DH
A4
A4
A3
A3
A3
A4
t
t
t
HI
HI
HI
t
t
t
LO
LO
LO
A2
A2
A5
2/n1
A1
A1
t
t
t
CLK
CLK
CLK
–18–
R/nW
A0
A0
t
t
t
DV
DV
DV
features include two auxiliary ADCs, a programmable sigma-delta
output, three auxiliary DACs, integrated clock circuitry to generate
all internal clocks, and buffered output clocks from a single input
reference.
The AD9860/AD9862 system functionality is described in the
following four sections: the Transmit Block, Receive Block, Timing
Generation Block, and the Auxiliary Function Block. The following
sections provide a brief description of the blocks and applications
for the four sections.
TRANSMIT SECTION COMPONENTS
The transmit block (Tx) accepts and can process real or complex
data. The Tx interface is configurable for a variety of data formats
and has special processing options such as interpolation and Hilbert
filters. A detailed block diagram of the AD9860/AD9862 transmit
path is shown in Figure 3. The transmit block diagram is broken
into these stages: DAC (Block A), Coarse Modulation (Block B),
D7
D7
D0
D1
D6
D6
OUTPUT REGISTER DATA
OUTPUT REGISTER DATA
OUTPUT REGISTER DATA
D2
D5
D5
D3
D4
D4
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D4
D3
D3
D5
D2
D2
D6
D1
D1
D7
D0
D0
t
t
t
H
H
H
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