AD9860 Analog Devices, AD9860 Datasheet
AD9860
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AD9860 Summary of contents
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... The AD9860 has 10-bit ADCs and 12-bit DACs; the AD9862 has 12-bit ADCs and 14-bit DACs. The AD9860/AD9862 receive path (Rx) consists of two channels ...
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... MHz Analog Out OUT 1 MHz Analog Out OUT 6 MHz Analog Out OUT AD9860 Narrowband SFDR (1 MHz Window) 1 MHz Analog Out OUT 1 MHz Analog Out OUT AD9862 Signal-to-Noise Ratio (SNR) AD9862 Signal-to-Noise and Distortion Ratio ...
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... Rx (Both Channels, Input Buffer Enabled) Rx (Both Channels, Input Buffer Disabled) Rx (32 MSPS, Low Power Mode, Buffer Disabled) Rx (16 MSPS, Low Power Mode, Buffer Disabled) Rx Path Powered Down DLL Digital Supply Current AD9860 Both Rx and Tx Path (All Channels Enabled) 2 Interpolation MSPS DAC ADC ...
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... III 25ºC III 25ºC III 25ºC III 25ºC III 25ºC III 25ºC III 25ºC III 25ºC III 25ºC III –4– AD9860/AD9862 Min Typ Max 18.5 AD9860/AD9862 Min Typ Max 5 2 128 5 ...
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... AD9860PCB AD9862PCB *The AD9860/AD9862 have been characterized to operate over the industrial temperature range (– +85 C) when operated in Half Duplex Mode. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9860/AD9862 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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... AGND 29 IOUT+B 30 IOUT–B AGND 31 32 AVDD DVDD 33 DGND 34 DGND 35 DVDD 36 37 Tx11/13 (MSB) Tx10/ CONNECT PIN CONFIGURATION AD9860/AD9862 TOP VIEW (Not to Scale) –6– REFB_B 102 REFT_B 101 100 AGND AVDD 99 98 AVDD AUX_SPI_csb 97 AUX_SPI_clk 96 AUX_SPI_do 95 DGND 94 DVDD 93 RxSYNC ...
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... AUX_ADC_A2 Auxiliary ADC A Input 2 126 AUX_ADC_B1 125 AUX_ADC_B2 127 AUX_ADC_REF Auxiliary ADC Reference –7– AD9860/AD9862 Function DLL Lock Indicator Pin DLL Analog Ground Pins No Connect DLL Analog Supply Pin Single Ended Input Clock (or Crystal Oscillator Input) Crystal Oscillator Input ...
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... The rms output noise is measured using histogram techniques. The ADC output code’s standard deviation is calculated in LSB and converted to an equivalent voltage. This results in a noise figure that can be referred directly to the input of the AD9860/ AD9862. Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio ...
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... MHz OUT TPC 7. TxDAC Harmonic Distortion vs. f OUT REV. 0 Typical Performance Characteristics–AD9860/AD9862 32MSPS DATA –10 4 INTERPOLATION –20 –30 –40 –50 –60 –70 –80 –90 –100 ...
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... LOW POWER MODE 2, BUFFER BYPASSED, 2V p-p INPUT, 1 RxPGA GAIN 60 BUFFER BYPASSED RxPGA GAIN LOW POWER 48 BUFFER ENABLED, MODE 2, 1V p-p INPUT, BUFFER ENABLED RxPGA GAIN 1V p-p INPUT, 2 RxPGA GAIN 100 150 200 250 300 f – MHz IN TPC 18. AD9860 Rx SINAD vs MSPS IN REV. 0 ...
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... MHz IN TPC 21. Rx THD vs MSPS ADC –50 AD9860 LOW POWER MODE 2, BUFFER BYPASSED, 1V p-p –55 INPUT, 2 RxPGA GAIN –60 AD9860 LOW POWER MODE 2, BUFFER ENABLED, –65 1V p-p INPUT, 2 RxPGA GAIN –70 –75 AD9862 LOW POWER MODE 2, BUFFER BYPASSED, – ...
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... AD9860/AD9862 2 Register Name Address Bit 7 General 0 SDIO BiDir Rx Power Down 1 V (diff) REF Byp Buffer Byp Buffer B Rx Misc Digital 6 RSV 7 Tx Power Down 8 RSV Offset 10 DAC A Offset [1: Offset Offset 12 DAC B Offset [1: Offset ...
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... Dual Port Mode, (i.e., non Rx Mux Mode). When in Rx Mux Mode, both Rx channels share the same output data bus, pins D0A to D9A (for AD9860) or D0A to D11A (for AD9862). The other Rx output bus (pins D0B to D9B or D0B to D11B) outputs a low logic. ...
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... AD9860/AD9862 Setting this bit high enables the decimation filters and decimates the receive data by two. REGISTER 8: Tx PWRDWN BIT 5: Alt Timing Mode The timing section in the data sheet describes two timing modes, the “Normal Operation” and the “Alternate Operation” modes. ...
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... DAC REGISTER 24: DLL BIT 6: Input Clock Control This bit defines what type of clock will be driving the AD9860/ AD9862. The default state is low, which allows either crystal con- nected to OSC1 and OSC2 or single-ended reference clock driving OSC1 to drive the internal timing circuits crystal will not be used, the internal oscillator should be disabled after power-up by setting this bit high ...
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... Register 50 can be set to 0x9E; this will reduce Rx AVDD power consumption by about 60% relative to nominal. REGISTER 63: CHIP ID BIT 7–0: Rev ID This read only register indicates the revision of the AD9860/AD9862. Reserved Registers Reserved registers are held for future development and should never be written to. ...
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... Blank registers, i.e., the registers with 0 settings and no indicated function, are placeholders used throughout the register map for spacing the AD9860/AD9862 control bits in a logic fashion and, potentially can be used for future development. A low should always be written to these registers if a write needs to take place. ...
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... The Tx interface is configurable for a variety of data formats and has special processing options such as interpolation and Hilbert filters. A detailed block diagram of the AD9860/AD9862 transmit path is shown in Figure 3. The transmit block diagram is broken into these stages: DAC (Block A), Coarse Modulation (Block B), – ...
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... It suppresses out-of-band signals more from the OUTFS and has a flat passband response (less than 0.1 dB ripple) extend- ing to 38% of the AD9860/AD9862 input Tx data rate (19% of the DAC update rate MSPS per channel when using 2 interpolation. –19– ...
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... TRANSMIT APPLICATIONS SECTION 0.7 0.8 0.9 1.0 The AD9860/AD9862 transmit path (Tx) includes two, high speed high performance, 12-/14-bit TxDACs. Figure 3 shows a detailed Interpolation Filter block diagram of the transmit data path and can be referred to throughout the explanation of the various modes of operation. ...
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... The coarse modulator and fine modulator can both be used and provide a tuning range between ± 68% of the DAC Nyquist frequency. If all Tx DSP blocks are bypassed, the AD9860/AD9862 oper- ates similar to a standard TxDAC. In Single Channel DAC Data mode, only the Channel A DAC is used; Channel B is powered down to reduce power consumption ...
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... The last stage simply consists of a flash A/D. A stable and accurate 1.0 V bandgap voltage reference is built into the AD9860/AD9862 and is used to set p-p differential input range. The internally generated reference should be decoupled pin using and a 0.1 mF capacitor in parallel ...
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... REF is on the output bus. RECEIVE APPLICATIONS SECTION The AD9860/AD9862 receive path (Rx) includes two high speed, high performance, 10-/12-bit ADCs. Figure 6 shows a detailed block diagram of the Rx data path and can be referred to through- out the explanation of the various modes of operation. The various ...
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... An internal Duty Cycle Stabilizer (DCS) can be enabled on the AD9860 by setting the Clk Duty register. This provides a stable 50% duty cycle to the ADC for high speed clock rates between 40 MSPS to 64 MSPS when proper duty cycle is more critical. ...
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... Figure 9. Rx Timing Diagram DLL MULT CLKOUT2 DIV B/2 01 C/2 10 B/4 10 C/4 CLKOUT2 –25– AD9860/AD9862 Table Ib. CLKSEL Set Logic High ADC See Figure 8 for Div 2 Decimate Multiplex Relative Timing Timing No Mux Rx Data = CLKOUT1 CLKOUT1 = CLKIN No Timing No. 4 ...
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... AD9860/AD9862 For the Normal Operation mode, the Tx timing is based on a clock derived from the DLL output, while the Rx clock is unaffected by the DLL setting. The Alternative Operation mode, timing utilizes the output of the DLL to generate both Rx and Tx clocks. It also sets default operation of the DLL to 4 mode. ...
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... Tx path timing, Tx digital processing options other than interpolation are ignored because they do not change data timing; Tx data timing reflects whether single or dual channel data is latched into the AD9860/AD9862. The rates of CLKOUT2 (and the input data rate) are related to CLKIN by the DLL Multiplier Register, the setting of the CLKOUT2 Divide Factor Register and the register ADC Div2 ...
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... Tx path are affected by the various register settings. For dual Tx data, an option to redirect demultiplexed data to either path is available. For example, the AD9860/AD9862 can accept complex data in the form of I then Q data or Q then I data, controlled through QI Order register. ...
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... –29– AD9860/AD9862 ...
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... Tx path are affected by the various register settings. For dual Tx data, an option to redirect demultiplexed data to either path is available. For example, the AD9860/AD9862 can accept complex data in the form of I then Q data or Q then I data, controlled through QI Order register. ...
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... AUX SPI runs rate of 16 MHz. REV. 0 AUX DAC The AD9860/AD9862 has three 8-bit voltage output auxiliary DACs, AUX DACs. The AUX DACs are available for supplying various control voltages throughout the system such as a VCXO voltage control or external VGA gain control and can typically sink or source ...
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... AD9860/AD9862 10 6 1.45 2 1.40 1.35 SEATING PLANE VIEW A ROTATED 90 CCW OUTLINE DIMENSIONS 128-Lead Plastic Quad Flatpack [LQFP] (ST-128B) Dimensions shown in millimeters 1.60 0.75 MAX 0.60 0.45 128 1 SEATING PLANE 0.20 0.09 VIEW 0.08 MAX COPLANARITY 0.50 BSC COMPLIANT TO JEDEC STANDARDS MS-026BHB –32– 16.00 BSC 14.00 BSC 103 102 20.00 BSC TOP VIEW (PINS DOWN) 22 ...