AD9866 Analog Devices, AD9866 Datasheet - Page 42

• Manufacturer Part Number: AD9866
• Manufacturer: Analog Devices

Specifications of AD9866

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Nibble
• Analog Input Type: Diff-Uni
• Ain Range: 6.3 V p-p,8 mV p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9866
The ADC is based on a pipeline architecture with each stage
consisting of a switched capacitor amplifier. Therefore, its per-
formance vs. bias level is mostly dependent on the sample rate.
Figure 83 shows how the typical current consumption seen at
AVDD (Pin 35 and Pin 40) varies as a function of Bits (2:0) and
sample rate, while the remaining bits are maintained at the
default setting of 0. Setting Bit 4 or Register 0x07 corresponds
to the 011 setting, and the settings of 101 and 111 result in
higher current consumption. Figure 84 shows how the SNR and
THD performance are affected for a 10 MHz sine wave input
for the lower power settings as the ADC sample rate is swept
from 20 MHz to 80 MHz.
A sine wave input is a standard and convenient method of
analyzing the performance of a system. However, the amount of
power reduction that is possible is application dependent, based
on the nature of the input waveform (such as frequency content,
peak-to-rms ratio), the minimum ADC sample, and the mini-
mum acceptable level of performance. Thus, it is advisable that
power-sensitive applications optimize the power bias setting of
the Rx path using an input waveform that is representative of
the application.
Figure 84. SNR and THD Performance vs. f
65
64
63
62
61
60
59
58
57
56
55
Figure 83. AVDD Current vs. ADC Bias Setting and Sample Rate
220
210
200
190
180
170
160
150
140
130
120
20
20
RxPGA = 0 dB, f
30
SNR-000
SNR-001
SNR-010
SNR-011
SNR-100
SNR-101
30
40
SAMPLE RATE (MSPS)
THD-000
THD-001
THD-010
THD-011
THD-100
THD-101
40
SAMPLE RATE (MSPS)
IN
= 10 MHz, AIN = −1 dBFS
101 OR 111
100
50
50
001
011
010
000
ADC
60
and ADC Bias Setting with
60
101
70
70
80
–54
–56
–58
–60
–62
–64
–66
–68
–70
–72
–74
80
Rev. B | Page 42 of 48
POWER DISSIPATION
The power dissipation of the AD9866 can become quite high in
full-duplex applications in which the Tx and Rx paths are si-
multaneously operating with nominal power bias settings. In
fact, some applications that use the IAMP may need to either
reduce its peak power capabilities or reduce the power con-
sumption of the Rx path, so that the device’s maximum
allowable power consumption, P
P
does not exceed 125
specification is based on the 64-pin LFSCP having a thermal
resistance, θ
30.8
application’s maximum ambient temperature, T
85
mined by the following equation:
Assuming the IAMP’s common-mode bias voltage is operating
off the same analog supply as the AD9866, the following equa-
tion can be used to calculate the maximum total current
consumption, I
With an ambient temperature of up to 85°C, I
If the IAMP is operating off a different supply or in the voltage
mode configuration, first calculate the power dissipated in the
IAMP, P
late I
Figure 78, Figure 79, Figure 81, and Figure 83 can be used to
calculate the current consumption of the Rx and Tx paths for a
given setting.
MODE SELECT UPON POWER-UP AND RESET
The AD9866 power-up state is determined by the logic levels
appearing at the MODE and CONFIG pins. The MODE pin is
used to select a half- or full-duplex interface by pin strapping it
low or high, respectively. The CONFIG pin is used in conjunc-
tion with the MODE pin to determine the default settings for
the SPI registers as outlined in Table 10.
The intent of these particular default settings is to allow some
applications to avoid using the SPI (disabled by pin-strapping
SEN high), thereby reducing implementation costs. For
example, setting MODE low and CONFIG high configures the
AD9866 to be backward-compatible with the AD9975, while
setting MODE high and CONFIG low makes it backward-
compatible with the AD9875. Other applications must use the
SPI to configure the device.
MAX
o
C, the maximum allowable power dissipation can be deter-
o
P
I
C/W, if the heat slug remains unsoldered.) If a particular
MAX
is specified at 1.66 W to ensure that the die temperature
MAX
MAX
, using Equation 14.
IAMP
= (P
= 1.66 + (85 − T
, using Equation 2 or Equation 5, and then recalcu-
JA
, of 24
MAX
MAX
− P
, of the IC:
o
o
C/W with its heat slug soldered. (The θ
IAMP
C at an ambient temperature of 85
)/3.47
A
)/24
MAX
, is not exceeded.
MAX
A
, falls below
is 478 mA.
o
C. This
JA
(13)
(14)
is