AD9866 Analog Devices, AD9866 Datasheet - Page 29

• Manufacturer Part Number: AD9866
• Manufacturer: Analog Devices

Specifications of AD9866

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Nibble
• Analog Input Type: Diff-Uni
• Ain Range: 6.3 V p-p,8 mV p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

TxDAC AND IAMP ARCHITECTURE
The Tx path contains a TxDAC with a current amplifier, IAMP.
The TxDAC reconstructs the output of the interpolation filter
and sources a differential current output that can be directed to
an external load or fed into the IAMP for further amplification.
The TxDAC’s and IAMPS’s peak current outputs are digitally
programmable over a 0 to −7.5 dB and 0 to −19.5 dB range,
respectively, in 0.5 dB increments. Note that this assumes
default register settings for Register 0x10 and Register 0x11.
Applications demanding the highest spectral performance
and/or lowest power consumption can use the TxDAC output
directly. The TxDAC is capable of delivering a peak signal
power-up to 10 dBm while maintaining respectable linearity
performance, as shown in Figure 27 through Figure 38. For
power-sensitive applications requiring the highest Tx power
efficiency, the TxDAC’s full-scale current output can be reduced
to as low as 2 mA, and its load resistors sized to provide a
suitable voltage swing that can be amplified by a low-power op
amp-based driver.
Most applications requiring higher peak signal powers (up to
23 dBm) should consider using the IAMP. The IAMP can be
configured as a current source for loads having a well defined
impedance (50 Ω or 75 Ω systems), or a voltage source (with the
addition of a pair of npn transistors) for poorly defined loads
having varying impedance (such as power lines).
Figure 62 shows the equivalent schematic of the TxDAC and
IAMP. The TxDAC provides a differential current output
appearing at IOUTP+ and IOUTP−. It can be modeled as a
differential current source generating a signal-dependent ac
current, when ΔI
current sources, sourcing a standing current equal to I. The full-
scale output current, IOUTFS, is equal to the sum of these
standing current sources (IOUTFS = 2 × I).
R
SET
0.1μF
I + ΔI
I – ΔI
Figure 62. Equivalent Schematic of TxDAC and IAMP
REFADJ
IOUTP+
IOUTP–
REFIO
S
has a peak current of I along with two dc
I
TxDAC
±ΔI
I
OFF1
S
I
I
OFF1
xN
IAMP
xN
I
OFF2
xG
I
OFF2
xG
Rev. B | Page 29 of 48
The value of I is determined by the R
pin along with the Tx path’s digital attenuation setting. With
0 dB attenuation, the value of I is
For example, an R
10.0 mA with IOUTFS equal to 20.0 mA. Note that the REFIO
pin provides a nominal band gap reference voltage of 1.23 V and
should be decoupled to analog ground via a 0.1 μF capacitor.
The differential current output of the TxDAC is always con-
nected to the IOUTP pins, but can be directed to the IAMP by
clearing Bit 0 of Register 0x0E. As a result, the IOUTP pins
must remain completely open, if the IAMP is to be used. The
IAMP contains two sets of current mirrors that are used to
replicate the TxDAC’s current output with a selectable gain. The
first set of current mirrors is designated as the primary path,
providing a gain factor of N that is programmable from 0 to 4 in
steps of 1 via Bits 2:0 of Register 0x10 with a default setting of
N = 4. Bit 7 of this register must be set to overwrite the default
settings of this register. This differential path exhibits the best
linearity performance (see Figure 42) and is available at the
IOUTN+ and IOUTN− pins. The maximum peak current per
output is 100 mA and occurs when the TxDAC’s standing
current, I, is set for 12.5 mA (IOUTFS = 25 mA).
The second set of current mirrors is designated as the secon-
dary path providing a gain factor of G that is programmable
from 0 to 36 via Bits 6:4 of Register 0x10, and Bits 6:0 of Register 0x11
with a default setting of G = 12. This differential path is intended
to be used in the voltage mode configuration to bias the external
npn transistors, because it exhibits degraded linearity perform-
ance (see Figure 43) relative to the primary path. It is capable of
sinking up to 180 mA of peak current into either its IOUTG+ or
IOUTG− pins. The secondary path actually consists of three
gain stages (G1, G2, and G3), which are individually programmable
as shown in Table 19. While many permutations may exist to
provide a fixed gain of G, the linearity performance of a
secondary path remains relatively independent of the various
individual gain settings that are possible to achieve a particular
overall gain factor.
Both sets of mirrors sink current, because they originate from
NMOS devices. Therefore, each output pin requires a dc current
path to a positive supply. Although the voltage output of each
output pin can swing between 0.5 V and 7 V, optimum ac per-
formance is typically achieved by limiting the ac voltage swing
with a dc bias voltage set between 4 V to 5 V. Lastly, both the
standing current, I, and the ac current, ΔI
amplified by the gain factor (N and G) with the total standing
current drawn from the positive supply being equal to
Programmable current sources I
can be used to improve the primary and secondary path mirrors’
linearity performance under certain conditions by increasing
their signal-to-standing current ratio. This feature provides a
I = 16 × (1.23/R
2 × (N + G) × I
SET
SET
value of 1.96 kΩ results in I equal to
)
OFF1
and I
SET
value at the REFADJ
OFF2
S
, from the TxDAC are
via Register 0x12
AD9866
(1)