AD7667 Analog Devices, AD7667 Datasheet - Page 24

• Manufacturer Part Number: AD7667
• Manufacturer: Analog Devices

Specifications of AD7667

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,2.5V p-p,Uni (Vref),Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7667
SLAVE SERIAL INTERFACE
External Clock
The AD7667 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/ INT pin is
held HIGH. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS . When CS and
RD are both LOW, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally HIGH or normally LOW when
inactive. Figure 41 and Figure 42 show the detailed timing
diagrams of these methods. Usually, because the AD7667 has a
longer acquisition phase than conversion phase, the data are
read immediately after conversion.
SDOUT
CNVST
SDOUT
BUSY
SCLK
BUSY
SCLK
SDIN
CS
RD
t
16
Figure 42. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
t
t
t
31
16
3
t
t
31
33
X
X
t
Figure 41. Slave Serial Data Timing for Reading (Read after Convert)
36
t
1
36
1
t
35
t
D15
t
35
37
D15
t
X15
37
t
34
2
2
EXT/INT = 1
D14
t
D14
X14
EXT/INT = 1
32
t
32
3
3
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D13
X13
D13
INVSCLK = 0
While the AD7667 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7667 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
is a discontinuous clock that is toggling only when BUSY is
LOW, or, more importantly, that it does not transition during
the latter half of BUSY HIGH.
INVSCLK = 0
14
14
15
15
D1
X1
D1
RD = 0
16
16
RD = 0
D0
X0
D0
17
X15
Y15
18
X14
Y14