AD7667 Analog Devices, AD7667 Datasheet - Page 21

• Manufacturer Part Number: AD7667
• Manufacturer: Analog Devices

Specifications of AD7667

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,2.5V p-p,Uni (Vref),Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

CONVERSION CONTROL
Figure 33 shows the detailed timing diagrams of the conversion
process. The AD7667 is controlled by the CNVST signal, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. CNVST operates independently of CS and RD .
In Impulse mode, conversions can be automatically initiated. If
CNVST is held LOW when BUSY is LOW, the AD7667 controls
the acquisition phase and automatically initiates a new con-
version. By keeping CNVST LOW, the AD7667 keeps the
conversion process running by itself. It should be noted that the
analog input must be settled when BUSY goes LOW. Also, at
power-up, CNVST should be brought LOW once to initiate the
conversion process. In this mode, the AD7667 can run slightly
faster than the guaranteed 666 kSPS limits in Impulse mode.
This feature does not exist in Warp and Normal modes.
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing.
The CNVST trace should be shielded with ground and a low
value serial resistor (e.g., 50 Ω) termination should be added
close to the output of the component that drives this line.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This can be achieved by using a dedicated
oscillator for CNVST generation, or by clocking CNVST with a
high frequency, low jitter clock, as shown in Figure 26.
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CS = RD = 0
MODE
CNVST
CNVST
BUSY
RESET
CNVST
BUSY
BUSY
DATA
DATA
BUS
Figure 35. Master Parallel Data Timing for Reading (Continuous Read)
ACQUIRE
t
t
3
5
t
3
t
Figure 33. Basic Conversion Timing
PREVIOUS CONVERSION DATA
CONVERT
1
t
7
Figure 34. RESET Timing
t
4
t
t
1
9
t
2
t
6
t
10
ACQUIRE
t
t
4
8
t
8
t
11
AD7667
NEW DATA
CONVERT