AD7921 Analog Devices, AD7921 Datasheet - Page 23

• Manufacturer Part Number: AD7921
• Description: 2-Channel, 2.35 V to 5.25 V, 250 kSPS, 12-Bit A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7921

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOP,SOT

For example, the ADSP-2189 has a master clock frequency of
40 MHz. If the SCLKDIV register is loaded with the value of 3,
then an SCLK of 5 MHz is obtained, and eight master clock
periods elapse for every one SCLK period. Depending on the
throughput rate selected, if the timer register is loaded with the
value 803 (803 + 1 = 804), then 100.5 SCLK occur between
interrupts and subsequently between transmit instructions. This
situation results in nonequidistant sampling, because the
transmit instruction occurs on a SCLK edge. If the number of
SCLKs between interrupts is a whole integer figure of N, then
equidistant sampling is implemented by the DSP.
AD7911/AD7921 to DSP563xx Interface
The connection diagram in Figure 34 shows how the AD7911/
AD7921 can be connected to the SSI (synchronous serial
interface) of the DSP563xx family of DSPs from Motorola. The
SSI is operated in synchronous and normal mode (SYN = 1 and
MOD = 0 in the Control Register B, CRB) with internally
generated word frame sync for both Tx and Rx (Bits FSL1 = 0
and FSL0 = 0 in the CRB). Set the word length in the Control
Register A (CRA) to 16 by setting Bits WL2 = 0, WL1 = 1, and
WL0 = 0 for the AD7921. This DSP does not offer the option
for a 14-bit word length, so the AD7911 word length is set up to
16 bits like the AD7921. For the AD7911, the conversion
process uses 16 SCLK cycles, with the last two clock periods
clocking out two trailing zeros to fill the 16-bit word.
To implement the power-down mode on the AD7911/AD7921,
the word length can be changed to 8 bits by setting Bits
WL2 = 0, WL1 = 0, and WL0 = 0 in CRA. The FSP bit in the
CRB register can be set to 1, which means that the frame goes
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low and a conversion starts. Likewise, by means of the Bits
SCD2, SCKD, and SHFD in the CRB register, the Pin SC2 (the
frame sync signal) and SCK in the serial port are configured as
outputs, and the MSB is shifted first.
The values are as follows:
Note that, for signal processing applications, the frame
synchronization signal from the DSP563xx must provide
equidistant sampling.
*ADDITIONAL PINS OMITTED FOR CLARITY
MOD = 0
SYN = 1
WL2, WL1, WL0 depend on the word length
FSL1 = 0, FSL0 = 0
FSP = 1, negative frame sync
SCD2 = 1
SCKD = 1
SHFD = 0
AD7921*
AD7911/
DOUT
SCLK
DIN
CS
Figure 34. Interfacing to the DSP563xx
AD7911/AD7921
SCK
SRD
STD
SC2
DSP563xx*