AD7938-6 Analog Devices, AD7938-6 Datasheet - Page 7

• Manufacturer Part Number: AD7938-6
• Description: 8-Channel, 625 kSPS, 12-Bit Parallel ADCs with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7938-6

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 625kSPS
• Interface: Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Description
Pin No.
1 to 8
9
10
11
12 to 14
15
16
17
18
Mnemonic
DB0 to DB7
V
DGND
DB8/HBEN
DB9 to DB11
BUSY
CLKIN
CONVST
WR
DRIVE
Description
Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result and allow the
control and shadow registers to be programmed. These pins are controlled by CS, RD, and WR. The logic
high/low voltage levels for these pins are determined by the V
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of
the AD7938-6 operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that
at V
Digital Ground. This is the ground reference point for all digital circuitry on the AD7938-6. This pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled
by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of
data being written to or read from the AD7938-6 is on DB0 to DB7. When HBEN is high, the top four bits of the
data being written to or read from the AD7938-6 are on DB0 to DB3. When reading from the device, DB4 to DB6
of the high byte contains the ID of the channel to which the conversion result corresponds (see the channel
address bits in
Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and allow the
control and shadow registers to be programmed in word mode. These pins are controlled by CS, RD, and WR.
The logic high/low voltage levels for these pins are determined by the V
Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the
falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and
the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode
just prior to the falling edge of BUSY on the 13
Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7938-6 takes 13 clock cycles + t
conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock.
Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from
track mode to hold mode on the falling edge of CONVST and the conversion process is initiated at this point.
Following power-down, when operating in autoshutdown or autostandby modes, a rising edge on CONVST is
used to power up the device.
Write Input. Active low logic input used in conjunction with CS to write data to the internal registers.
DD
but should never exceed V
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE UNDERSIDE OF
Table 9
THE PACKAGE. CONNECT THE EPAD TO THE GROUND PLANE
OF THE PCB USING MULTIPLE VIAS.
1
2
3
4
5
6
7
8
). When writing to the device, DB4 to DB7 of the high byte must be all 0s.
32
9
PIN 1
IDENTIFIER
31
10
30
11
Figure 2. Pin Configuration
(Not to Scale)
AD7938-6
TOP VIEW
DD
29
12
Rev. C | Page 7 of 32
2
. The frequency of the master clock input therefore determines the
by more than 0.3 V.
28
13
27
14
26
15
25
16
th
rising edge of CLKIN (see
24
23
22
21
20
19
18
17
V
V
V
AGND
CS
RD
WR
CONVST
IN
IN
REFIN
1
0
/V
REFOUT
DRIVE
input.
DRIVE
Figure 35
input.
).
AD7938-6