AD7266 Analog Devices, AD7266 Datasheet - Page 21

• Manufacturer Part Number: AD7266
• Description: Differential/Single-Ended Input, Dual, Simultaneous Sampling, 2 MSPS, 12-Bit, 3-Channel SAR A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7266

• Resolution (bits): 12bit
• # Chan: 12
• Sample Rate: 2MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,(Vref) p-p,2.5V p-p,5V p-p,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

POWER-UP TIMES
As described in detail, the AD7266 has two power-down
modes, partial power-down and full power-down. This section
deals with the power-up time required when coming out of
either of these modes. It should be noted that the power-up
times, as explained in this section, apply with the recommended
capacitors in place on the D
To power up from full power-down, approximately 1.5 ms
should be allowed from the falling edge of CS , shown as
t
requires much less time. The power-up time from partial
power-down is typically 1 μs; however, if using the internal
reference, then the AD7266 must be in partial power-down for
at least 67 μs in order for this power-up time to apply.
When power supplies are first applied to the AD7266, the ADC
may power up in either of the power-down modes or normal
mode. Because of this, it is best to allow a dummy cycle to
elapse to ensure the part is fully powered up before attempting a
valid conversion. Likewise, if it is intended to keep the part in
the partial power-down mode immediately after the supplies are
applied, then two dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the 10
edge (see
high before the 10
falling edge (see
place the part in full power-down mode when the supplies are
applied, then three dummy cycles must be initiated. The first
dummy cycle must hold
edge (see
the part in full power-down (see
Once supplies are applied to the AD7266, enough time must be
allowed for any external reference to power up and charge the
various reference buffer decoupling capacitors to their final values.
POWER vs. THROUGHPUT RATE
The power consumption of the AD7266 varies with the
throughput rate. When using very slow throughput rates and as
fast an SCLK frequency as possible, the various power-down
options can be used to make significant power savings.
However, the AD7266 quiescent current is low enough that
POWER-UP2
in
Figure 34
Figure 34
Figure 38
D
D
SCLK
OUT
OUT
CS
Figure 35
A
B
th
); in the second cycle,
); the second and third dummy cycles place
SCLK edge but after the second SCLK
. Powering up from partial power-down
CS low until after the 10
). Alternatively, if it is intended to
1
CAP
A and D
THE PART BEGINS
TO POWER UP.
Figure 37
CAP
INVALID DATA
CS must be brought
B pins.
).
t
POWER-UP2
th
th
SCLK falling
SCLK falling
Figure 38. Exiting Full Power-Down Mode
10
Rev. B | Page 21 of 28
14
even without using the power-down options, there is a
noticeable variation in power consumption with sampling rate.
This is true whether a fixed SCLK value is used or if it is scaled
with the sampling rate. Figure 39 and Figure 40 show plots of
power vs. the throughput rate when operating in normal mode
for a fixed maximum SCLK frequency and an SCLK frequency
that scales with the sampling rate with V
respectively. In all cases, the internal reference was used.
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
Figure 39. Power vs. Throughput in Normal Mode with V
Figure 40. Power vs. Throughput in Normal Mode with V
30
28
26
24
22
20
18
16
14
12
10
0
0
T
T
A
A
= 25°C
= 25°C
200
1
200
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION.
400
400
600
VALID DATA
VARIABLE SCLK
THROUGHPUT (kSPS)
THROUGHPUT (kSPS)
600
800
VARIABLE SCLK
24MHz SCLK
32MHz SCLK
1000 1200 1400 1600 1800
800
14
1000
DD
= 3 V and V
1200
1400
AD7266
DD
DD
2000
= 3 V
= 5 V
DD
= 5 V,