AD7266 Analog Devices, AD7266 Datasheet

no-image

AD7266

Manufacturer Part Number
AD7266
Description
Differential/Single-Ended Input, Dual, Simultaneous Sampling, 2 MSPS, 12-Bit, 3-Channel SAR A/D Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD7266

Resolution (bits)
12bit
# Chan
12
Sample Rate
2MSPS
Interface
Ser,SPI
Analog Input Type
Diff-Uni,SE-Uni
Ain Range
(2Vref) p-p,(Vref) p-p,2.5V p-p,5V p-p,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
Adc Architecture
SAR
Pkg Type
CSP,QFP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7266BSUZ
Manufacturer:
VIA
Quantity:
85
Part Number:
AD7266BSUZ
Manufacturer:
ADI
Quantity:
200
Part Number:
AD7266BSUZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD7266BSUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7266BSUZ-REEL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD7266BSUZ-REEL7
Manufacturer:
Analog Devices Inc
Quantity:
10 000
FEATURES
Dual 12-bit, 3-channel ADC
Throughput rate: 2 MSPS
Specified for V
Power consumption
Pin-configurable analog inputs
70 dB SNR at 50 kHz input frequency
Accurate on-chip reference: 2.5 V
Dual conversion with read 437.5 ns, 32 MHz SCLK
High speed serial interface
−40°C to +125°C operation
Shutdown mode: 1 μA maximum
32-lead LFCSP and 32-lead TQFP
1 MSPS version,
GENERAL DESCRIPTION
The AD7266
approximation ADC that operates from a single 2.7 V to 5.25 V
power supply and features throughput rates up to 2 MSPS. The
device contains two ADCs, each preceded by a 3-channel
multiplexer, and a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 30 MHz.
The conversion process and data acquisition use standard
control inputs allowing easy interfacing to microprocessors or
DSPs. The input signal is sampled on the falling edge of CS ;
conversion is also initiated at this point. The conversion time is
determined by the SCLK frequency. There are no pipelined
delays associated with the part.
The AD7266 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. With 5 V
supplies and a 2 MSPS throughput rate, the part consumes
6.2 mA maximum. The part also offers flexible power/
throughput rate management when operating in normal mode
as the quiescent current consumption is so low.
The analog input range for the part can be selected to be a 0 V
to V
complement output coding. The AD7266 has an on-chip 2.5 V
reference that can be overdriven when an external reference is
preferred. This external reference range is 100 mV to V
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
9 mW at 1.5 MSPS with 3 V supplies
27 mW at 2 MSPS with 5 V supplies
12-channel single-ended inputs
6-channel fully differential inputs
6-channel pseudo differential inputs
±0.2% maximum @ 25°C, 20 ppm/°C maximum
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
REF
(or 2 × V
1
is a dual, 12-bit, high speed, low power, successive
DD
REF
AD7265
of 2.7 V to 5.25 V
) range, with either straight binary or twos
DD
.
Differential/Single-Ended Input, Dual
2 MSPS, 12-Bit, 3-Channel SAR ADC
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
The AD7266 is available in a 32-lead LFCSP and a
32-lead TQFP.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
1
V
V
V
V
V
V
V
V
V
V
V
V
Protected by U.S. Patent No. 6,681,332
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
AGND AGND AGND D
Two Complete ADC Functions Allow Simultaneous
Sampling and Conversion of Two Channels.
Each ADC has three fully/pseudo differential pairs, or six
single-ended channels, as programmed. The conversion
result of both channels is simultaneously available on
separate data lines, or in succession on one data line if only
one serial port is available.
High Throughput with Low Power Consumption.
The AD7266 offers a 1.5 MSPS throughput rate with 11.4 mW
maximum power dissipation when operating at 3 V.
The AD7266 offers both a standard 0 V to V
and a 2 × V
No Pipeline Delay.
The part features two standard successive approximation
ADCs with accurate control of the sampling instant via a
CS input and once off conversion control.
REF SELECT
MUX
MUX
REF
FUNCTIONAL BLOCK DIAGRAM
BUF
BUF
T/H
T/H
REF
©2005–2011 Analog Devices, Inc. All rights reserved.
input range.
CAP
APPROXIMATION
APPROXIMATION
SUCCESSIVE
SUCCESSIVE
B
D
CONTROL
CAP
12-BIT
LOGIC
12-BIT
Figure 1.
ADC
ADC
A
DGND
AV
DD
AD7266
DRIVERS
DRIVERS
OUTPUT
OUTPUT
DGND
DV
DD
AD7266
www.analog.com
REF
input range
D
SCLK
CS
RANGE
SGL/DIFF
A0
A1
A2
V
D
OUT
DRIVE
OUT
A
B

Related parts for AD7266

AD7266 Summary of contents

Page 1

... High Throughput with Low Power Consumption. The AD7266 offers a 1.5 MSPS throughput rate with 11.4 mW maximum power dissipation when operating The AD7266 offers both a standard and a 2 × V input range ...

Page 2

... Power-Up Times......................................................................... 21 Power vs. Throughput Rate....................................................... 21 Serial Interface ................................................................................ 22 Microprocessor Interfacing........................................................... 23 AD7266 to ADSP218x ............................................................... 23 AD7266 to ADSP-BF53x ........................................................... 24 AD7266 to TMS320C541 .......................................................... 24 AD7266 to DSP563xx ................................................................ 25 Application Hints ........................................................................... 26 Grounding and Layout .............................................................. 26 PCB Design Guidelines for LFCSP .......................................... 26 Evaluating the AD7266 Performance ...................................... 26 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27 4/05—Revision 0: Initial Version Rev Page ...

Page 3

... REF V ± IN− CM REF V ± IN− CM REF Rev Page AD7266 = 4. 5. Test Conditions/Comments kHz sine wave; differential mode kHz sine wave; single-ended and IN pseudo differential modes kHz sine wave; differential mode kHz sine wave; single-ended and ...

Page 4

... AD7266 Parameter DC Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT 8 Reference Output Voltage Long-Term Stability 2 Output Voltage Hysteresis Reference Input Voltage Range DC Leakage Current Input Capacitance Output Impedance CAP CAP Reference Temperature Coefficient V Noise REF LOGIC INPUTS Input High Voltage, V INH ...

Page 5

... A A and D B are three-state disabled OUT OUT = high impedance OUT OUT high impedance OUT OUT high impedance OUT OUT ) and timed from a voltage level of 1 AD7266 ...

Page 6

... AD7266 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter V to AGND DGND DGND DRIVE V to AGND DRIVE AGND to DGND Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to GND V to AGND REF Input Current to Any Pin 1 Except Supplies ...

Page 7

... ADC A and ADC B. In addition, Pin D capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7266 through the Analog Supply Voltage, 2 5.25 V. This is the only supply voltage for all analog circuitry on the AD7266. The DD AV and transient basis ...

Page 8

... DGND. The voltage at this pin may be different than that at AV never exceed either by more than 0 Digital Supply Voltage, 2 5.25 V. This is the supply voltage for all digital circuitry on the AD7266. The DV DD and AV voltages should ideally be at the same potential and must not be more than 0.3 V apart even transient basis ...

Page 9

... CODE Figure 8. Typical DNL 1 5V DIFFERENTIAL MODE 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 500 1000 1500 2000 2500 3000 CODE Figure 9. Typical INL AD7266 = 3V DRIVE = 2MSPS 800 900 1000 = 3V DRIVE 3500 4000 = 3V DRIVE 3500 4000 ...

Page 10

... AD7266 1.0 V DIFFERENTIAL MODE 0.8 POSITIVE DNL 0.6 0.4 POSITIVE INL 0.2 0 –0.2 NEGATIVE INL –0.4 –0.6 NEGATIVE DNL –0.8 –1.0 0 0.5 1.0 1.5 V (V) REF Figure 10. Linearity Error vs. V 12.0 11.5 11 10.5 SINGLE-ENDED MODE 10 9.5 DD SINGLE-ENDED MODE 9 8.5 DD DIFFERENTIAL MODE DIFFERENTIAL MODE 8.0 7.5 7.0 0 0.5 1.0 1.5 2.0 2.5 3.0 V (V) REF Figure 11. Effective Number of Bits vs. V 2.5010 2 ...

Page 11

... N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB Therefore, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. For the AD7266 defined as THD where the rms amplitude of the fundamental. ...

Page 12

... AD7266 The AD7266 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. ...

Page 13

... CIRCUIT INFORMATION The AD7266 is a fast, micropower, dual, 12-bit, single-supply, ADC that operates from a 2 5.25 V supply. When operated from supply, the AD7266 is capable of throughput rates of 2 MSPS when provided with a 32 MHz clock, and a throughput rate of 1.5 MSPS The AD7266 contains two on-chip, differential track-and-hold amplifiers, two successive approximation ADCs, and a serial interface with two separate data output pins ...

Page 14

... These may be selected as described in the Analog Input Selection section. = 300Ω Single-Ended Mode The AD7266 can have a total of 12 single-ended analog input channels. In applications where the signal source has high = 0Ω impedance recommended to buffer the analog input before applying it to the ADC ...

Page 15

... V range, respectively. The common mode REF REF must be in this range to guarantee the functionality of the AD7266. When a conversion takes place, the common mode is rejected, resulting in a virtually noise free signal of amplitude −V +V corresponding to the digital codes 4096. If the REF 2 × ...

Page 16

... AD7266 Using an Op Amp Pair An op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the AD7266. The circuit configurations illustrated in Figure 26 and Figure 27 show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively ...

Page 17

... If the mode is changed from fully differential to pseudo differential, for example, then the acquisition time would start again from this point. The selected input channels are decoded as shown in Table 6. The analog input range of the AD7266 can be selected × V REF ...

Page 18

... V ± V Input Range REF REF DIGITAL INPUTS The digital inputs applied to the AD7266 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs can be applied and are not restricted by range is used. the V REF /4096 when the 0 V Maximum Ratings section for more information ...

Page 19

... OUT D B OUT th SCLK falling To exit this mode of operation and power up the AD7266 again, A and OUT a dummy conversion is performed. On the falling edge the device begins to power up and continues to power up as long held low until after the falling edge of the 10 SCLK. The device is fully powered up after approximately 1 μ ...

Page 20

... OUT Note that it is not necessary to complete the 14 SCLKs once CS is brought high to enter a power-down mode. To exit full power-down and power up the AD7266, a dummy conversion is performed, as when powering up from partial power-down. On the falling edge the device begins to power up and continues to power up, as long held low ...

Page 21

... AD7266 must be in partial power-down for at least 67 μs in order for this power-up time to apply. When power supplies are first applied to the AD7266, the ADC may power up in either of the power-down modes or normal mode. Because of this best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion ...

Page 22

... A minimum of 14 serial clock cycles are required to perform the conversion process and to access data from one conversion on either data line of the AD7266. CS going low provides the leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges, beginning with a second leading zero ...

Page 23

... MICROPROCESSOR INTERFACING The serial interface on the AD7266 allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7266 with some of the more common microcontroller and DSP serial interface protocols. AD7266 TO ADSP-218x The ADSP-218x family of DSPs interface directly to the AD7266 without any glue logic required ...

Page 24

... DSPs means only one serial port is necessary to read from both D pins simultaneously. Figure 44 shows both D OUT the AD7266 connected to Serial Port 0 of the OUT ADSP-BF53x. The SPORT0 Receive Configuration 1 register and SPORT0 Receive Configuration 2 register should be set up as outlined in Table 9 and Table 10. ...

Page 25

... AD7266 TO DSP563xx The connection diagram in Figure 46 shows how the AD7266 can be connected to the ESSI (synchronous serial interface) of the DSP563xx family of DSPs from Motorola. There are two on-board ESSIs, and each is operated in synchronous mode (Bit SYN = 1 in CRB register) with internally generated word length frame sync for both TX and RX (Bit FSL1 = 0 and Bit FSL0 = 0 in CRB) ...

Page 26

... However, the analog ground plane should be allowed to run under the AD7266 to avoid noise coupling. The power supply lines to the AD7266 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. ...

Page 27

... Z = RoHS Compliant Part. 2 The EVAL-AD7266CB can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL Board for evaluation/demonstration purposes. 3 The EVAL-CED1Z controller board allows control and communicate with all Analog Devices evaluation boards whose model numbers end in ED. ...

Page 28

... AD7266 NOTES ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04603-0-5/11(B) Rev Page ...

Related keywords