AD9287 Analog Devices, AD9287 Datasheet - Page 22

• Manufacturer Part Number: AD9287
• Description: Quad, 8-Bit, 100 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9287

• Resolution (bits): 8bit
• # Chan: 4
• Sample Rate: 100MSPS
• Interface: LVDS,Ser
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9287
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (f
due only to aperture jitter (t
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 47).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9287.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators are the
best clock sources. If the clock is generated from another type of
source (by gating, dividing, or another method), it should be
retimed by the original clock during the last step.
Refer to the AN-501 Application Note and to the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs at www.analog.com.
SNR Degradation = 20 × log 10(1/2 × π × f
130
120
110
100
90
80
70
60
50
40
30
1
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
Figure 47. Ideal SNR vs. Input Frequency and Jitter
ANALOG INPUT FREQUENCY (MHz)
10
J
) can be calculated by
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
100
A
× t
14 BITS
12 BITS
16 BITS
J
)
1000
Rev. E | Page 22 of 52
A
)
Power Dissipation and Power-Down Mode
As shown in Figure 48, the power dissipated by the AD9287 is
proportional to its sample rate. The digital power dissipation
does not vary significantly because it is determined primarily by
the DRVDD supply and bias current of the LVDS output drivers.
Figure 48. Supply Current vs. f
300
250
200
150
100
50
0
0
20
40
ENCODE (MSPS)
SAMPLE
60
for f
IN
DRVDD CURRENT
TOTAL POWER
AVDD CURRENT
= 10.3 MHz, f
80
100
Data Sheet
SAMPLE
= 100 MSPS
120
600
550
500
450
400
350
300