AD7951 Analog Devices, AD7951 Datasheet - Page 29

• Manufacturer Part Number: AD7951
• Manufacturer: Analog Devices

Specifications of AD7951

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Byte,Par,Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip 10V,Bip 5.0V,Uni 10V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

HARDWARE CONFIGURATION
The AD7951 can be configured at any time with the dedicated
hardware pins WARP, IMPULSE, BIPOLAR, TEN, OB/ 2C , and
PD for parallel mode (SER/ PAR = low) or serial hardware mode
(SER/ PAR = high, HW/ SW = high). Programming the AD7951
for mode selection and input range configuration can be done
before or during conversion. Like the RESET input, the ADC
requires at least one acquisition time to settle as indicated in
Figure 44. See Table 6 for pin descriptions. Note that these
inputs are high impedance when using the software
configuration mode.
SOFTWARE CONFIGURATION
The pins multiplexed on D[13:10] used for software configura-
tion are: HW/ SW , SCIN, SCCLK, and SCCS . The AD7951 is
programmed using the dedicated write-only serial configurable
port (SCP) for conversion mode, input range selection, output
coding, and power-down using the serial configuration register.
See Table 9 for details of each bit in the configuration register.
The SCP can only be used in serial software mode selected with
SER/ PAR = high and HW/ SW = low since the port is multiplexed
on the parallel interface.
The SCP is accessed by asserting the port’s chip select, SCCS ,
and then writing SCIN synchronized with SCCLK, which (like
SDCLK) is edge sensitive depending on the state of INVSCLK.
See Figure 45 for timing details. SCIN is clocked into the con-
figuration register MSB first. The configuration register is an
internal shift register that begins with Bit 8, the start bit. The 9
SPPCLK edge updates the register and allows the new settings to be
used. As indicated in the timing diagram, at least one acquisition
time is required from the 9
bits and are not written to while the SCP is being updated.
The SCP can be written to at any time, up to 40 MHz, and it is
recommended to write to while the AD7951 is not busy
converting, as detailed in Figure 45. In this mode, the full
1 MSPS is not attainable because the time required for SCP access
is (t
required, the SCP can be written to during conversion, however,
31
+ 9 × 1/SCCLK + t
8
BIPOLAR,
) minimum. If the full throughput is
IMPULSE
th
CNVST
WARP,
BUSY
SCCLK edge. Bits [1:0] are reserved
TEN
t
8
Figure 44. Hardware Configuration Timing
HW/SW = 0
Rev. 0 | Page 29 of 32
th
PD = 0
it is not recommended to write to the SCP during the last 450 ns
of conversion (BUSY = high), or performance degradation can
result. In addition, the SCP can be accessed in both serial master
and serial slave read during and read after convert modes.
Note that at power up, the configuration register is undefined.
The RESET input clears the configuration register (sets all bits
to 0), thus placing the configuration to 0 V to 5 V input, normal
mode, and twos complemented output.
Table 9. Configuration Register Description
Bit
8
7
6
5
4
3
2
1
0
SER/PAR = 0, 1
Name
START
BIPOLAR
TEN
PD
IMPULSE
WARP
OB/2C
RSV
RSV
Description
START bit. With the SCP enabled ( SCCS = low),
when START is high, the first rising edge of SCCLK
(INVSCLK = low) begins to load the register with
the new configuration.
Input Range Select. Used in conjunction with
Bit 6, TEN, per the following:
Input Range Select. See Bit 7, BIPOLAR.
Power Down.
PD = low, normal operation.
PD = high power down the ADC. The SCP is
accessible while in power down. To power up the
ADC, write PD = low on the next configuration
setting.
Mode Select. Used in conjunction with Bit 3,
WARP, per the following:
Mode Select. See Bit 4, IMPULSE.
Output Coding
OB/2C = low, use twos complement output.
OB/2C = high, use straight binary output.
Reserved.
Reserved.
Input Range
0 V to 5 V
0 V to 10 V
±5 V
±10 V
Mode
Normal
Impulse
Warp
Normal
t
8
WARP
Low
Low
High
High
BIPOLAR
Low
Low
High
High
IMPULSE
Low
High
Low
High
TEN
Low
1
Low
High
AD7951