AD7951 Analog Devices, AD7951 Datasheet - Page 27

• Manufacturer Part Number: AD7951
• Manufacturer: Analog Devices

Specifications of AD7951

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Byte,Par,Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip 10V,Bip 5.0V,Uni 10V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

SLAVE SERIAL INTERFACE
The pins multiplexed on D[19:2] used for slave serial
interface are: EXT/ INT , INVSCLK, SDIN, SDOUT,
SDCLK and RDERROR.
External Clock (SER/ PAR = High, EXT/ INT = High)
Setting the EXT/ INT = high allows the AD7951 to accept an
externally supplied serial data clock on the SDCLK pin. In this
mode, several methods can be used to read the data. The
external serial clock is gated by CS . When CS and RD are both
low, the data can be read after each conversion or during the
following conversion. A clock can be either normally high or
normally low when inactive. For detailed timing diagrams, see
Figure 42 and Figure 43.
While the AD7951 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins,
or degradation of the conversion result may occur. This is
particularly important during the last 450 ns of the conversion
phase because the AD7951 provides error correction circuitry
that can correct for an improper bit decision made during the
first part of the conversion phase. For this reason, it is recom-
mended that any external clock provided is a discontinuous
clock that transitions only when BUSY is low or, more importantly,
that it does not transition during the last 450 ns of BUSY high.
External Discontinuous Clock Data Read After
Conversion
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave modes.
Figure 42 shows the detailed timing diagrams for this method.
After a conversion is complete, indicated by BUSY returning low,
the conversion result can be read while both CS and RD are low.
Data is shifted out MSB first with 14 clock pulses and, depending
on the SDCLK frequency, can be valid on the falling and rising
edges of the clock.
One advantage of this method is that conversion performance is
not degraded because there are no voltage transients on the digital
interface during the conversion process. Another advantage is
the ability to read the data at any speed up to 40 MHz, which
accommodates both the slow digital host interface and the fastest
serial reading.
Daisy-Chain Feature
Also in the read after convert mode, the AD7951 provides a
daisy-chain feature for cascading multiple converters together
using the serial data input pin, SDIN. This feature is useful for
reducing component count and wiring connections when
desired, for instance, in isolated multiconverter applications.
See Figure 42 for the timing details.
An example of the concatenation of two devices is shown in
Figure 41.
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Simultaneous sampling is possible by using a common CNVST
signal. Note that the SDIN input is latched on the opposite edge
of SDCLK used to shift out the data on SDOUT (SDCLK falling
edge when INVSCLK = low). Therefore, the MSB of the
upstream converter follows the LSB of the downstream
converter on the next SDCLK cycle. In this mode, the 40 MHz
SDCLK rate cannot be used since the SDIN to SDCLK setup
time, t
SDOUT delay, t
simultaneously sampled). For proper operation, the SDCLK edge
for latching SDIN (or ½ period of SDCLK) needs to be:
Or the max SDCLK frequency needs to be:
If not using the daisy-chain feature, the SDIN input should
always be tied either high or low.
External Clock Data Read During Previous Conversion
Figure 43 shows the detailed timing diagrams for this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 14 clock pulses, and depending on the SDCLK
frequency, can be valid on both the falling and rising edges of
the clock. The 14 bits have to be read before the current
conversion is complete; otherwise, RDERROR is pulsed high
and can be used to interrupt the host interface to prevent
incomplete data reading.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 40 MHz is recommended to ensure
that all the bits are read during the first half of the SAR
conversion phase.
The daisy-chain feature should not be used in this mode since
digital activity occurs during the second half of the SAR
conversion phase, likely resulting in performance degradation.
CNVST IN
SCLK IN
t
f
1
Figure 41. Two AD7951 Devices in a Daisy-Chain Configuration
33
SDCLK
CS IN
2 /
RDC/SDIN
, is less than the minimum time specified. (SDCLK to
SDCLK
(UPSTREAM)
AD7951
=
BUSY
#2
=
( 2
32
t
t
, is the same for all converters when
SDOUT
32
CNVST
32
SCLK
1
+
+
CS
t
t
33
33
)
RDC/SDIN
(DOWNSTREAM)
AD7951
BUSY
#1
SDOUT
CNVST
SCLK
CS
AD7951
BUSY
OUT
DATA
OUT