AD7634 Analog Devices, AD7634 Datasheet - Page 27

• Manufacturer Part Number: AD7634
• Manufacturer: Analog Devices

Specifications of AD7634

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 670kSPS
• Interface: Byte,Par,Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: 10V p-p,20 V p-p,40 V p-p
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

SLAVE SERIAL INTERFACE
The pins multiplexed on D[13:6] used for slave serial inter-
face are: EXT/ INT , INVSCLK, SDIN, SDOUT, SDCLK, and
RDERROR.
External Clock (MODE[1:0] = 3, EXT/ INT = High)
Setting the EXT/ INT = high allows the AD7634 to accept an
externally supplied serial data clock on the SDCLK pin. In this
mode, several methods can be used to read the data. The external
serial clock is gated by CS . When CS and RD are both low, the
data can be read after each conversion or during the following
conversion. A clock can be either normally high or normally
low when inactive. For detailed timing diagrams, see
and
While the AD7634 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins,
or degradation of the conversion result may occur. This is par-
ticularly important during the last 550 ns of the conversion phase
because the AD7634 provides error correction circuitry that can
correct for an improper bit decision made during the first part
of the conversion phase. For this reason, it is recommended that
any external clock provided is a discontinuous clock that transi-
tions only when BUSY is low or, more importantly, that it does not
transition during the last 450 ns of BUSY high.
External Discontinuous Clock Data Read After
Conversion
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave modes.
Figure 44 shows the detailed timing diagrams for this method.
After a conversion is completed, indicated by BUSY returning low,
the conversion result can be read while both CS and RD are low.
Data is shifted out MSB first with 18 clock pulses and, depending
on the SDCLK frequency, can be valid on the falling and rising
edges of the clock.
One advantage of this method is that conversion performance is
not degraded because there are no voltage transients on the digital
interface during the conversion process. Another advantage is
the ability to read the data at any speed up to 40 MHz, which
accommodates both the slow digital host interface and the fastest
serial reading.
Daisy-Chain Feature
Also in the read after convert mode, the AD7634 provides a daisy-
chain feature for cascading multiple converters together using the
serial data input pin, SDIN. This feature is useful for reducing
component count and wiring connections when desired, for
instance, in isolated multiconverter applications. See Figure 44
for the timing details.
An example of the concatenation of two devices is shown in
Figure 43.
Figure 45
.
Figure 44
Rev. A | Page 27 of 32
Simultaneous sampling is possible by using a common CNVST
signal. Note that the SDIN input is latched on the opposite edge
of SDCLK used to shift out the data on SDOUT (SDCLK falling
edge when INVSCLK = low). Therefore, the MSB of the upstream
converter follows the LSB of the downstream converter on the
next SDCLK cycle. In this mode, the 40 MHz SDCLK rate cannot
be used because the SDIN-to-SDCLK setup time, t
the minimum time specified. (SDCLK-to-SDOUT delay, t
the same for all converters when simultaneously sampled.) For
proper operation, the SDCLK edge for latching SDIN (or ½
period of SDCLK) needs to be
Or the maximum SDCLK frequency needs to be
If not using the daisy-chain feature, the SDIN input should
always be tied either high or low.
External Clock Data Read During Previous Conversion
Figure 45 shows the detailed timing diagrams for this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 18 clock pulses, and depending on the SDCLK
frequency, data can be valid on both the falling and rising edges
of the clock. The 18 bits have to be read before the current
conversion is complete; otherwise, RDERROR is pulsed high
and can be used to interrupt the host interface to prevent
incomplete data reading.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 40 MHz is recommended to ensure
that all the bits are read during the first half of the SAR conver-
sion phase.
The daisy-chain feature should not be used in this mode because
digital activity occurs during the second half of the SAR conver-
sion phase likely resulting in performance degradation.
SDCLK IN
CNVST IN
t
f
CS IN
Figure 43. Two AD7634 Devices in a Daisy-Chain Configuration
1
SDCLK
2 /
RDC/SDIN SDOUT
SDCLK
(UPSTREAM)
AD7634
=
BUSY
#2
=
( 2
t
t
CNVST
SDCLK
32
32
1
+
+
CS
t
t
33
33
)
RDC/SDIN
(DOWNSTREAM)
AD7634
BUSY
#1
SDOUT
CNVST
SDCLK
CS
33
AD7634
, is less than
BUSY
OUT
DATA
OUT
32
, is