HA9P2556-9 Intersil, HA9P2556-9 Datasheet - Page 5

• Manufacturer Part Number: HA9P2556-9
• Description: IC MUX ANALOG 57MHZ MONO 16-SOIC
• Manufacturer: Intersil

Specifications of HA9P2556-9

• Function: Analog Multiplier
• Number Of Bits/stages: 4-Quadrant
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Simplified Schematic
Application Information
Operation at Reduced Supply Voltages
The HA-2556 will operate over a range of supply voltages,
±5V to ±15V. Use of supply voltages below ±12V will reduce
input and output voltage ranges. See “Typical Performance
Curves” on page 12 for more information.
Offset Adjustment
X-Channel and Y-Channel offset voltages may be nulled by
using a 20k potentiometer between the V
pin A and B and connecting the wiper to V-. Reducing the
channel offset voltage, will reduce AC feedthrough and
improve the multiplication error. Output offset voltage can
also be nulled by connecting V
potentiometer which is tied between V+ and V-.
Capacitive Drive Capability
When driving capacitive loads >20pF a 50Ω resistor should
be connected between V
output (see Figure 1). This will prevent the multiplier from
going unstable and reduce gain peaking at high frequencies.
The 50Ω resistor will dampen the resonance formed with the
capacitive load and the inductance of the output at Pin 8.
Gain accuracy will be maintained because the resistor is
inside the feedback loop.
Theory of Operation
The HA-2556 creates an output voltage that is the product
of the X and Y input voltages divided by a constant scale
factor of 5V. The resulting output has the correct polarity in
each of the four quadrants defined by the combinations of
positive and negative X and Y inputs. The Z stage provides
the means for negative feedback (in the multiplier
configuration) and an input for summation into the output.
V
V
XIO
X
+
OUT
A
and V
5
Z
- to the wiper of a
V
XIO
Z
V
+, using V
X
V
-
B
BIAS
YIO
or V
+
-
Z
+ as the
XIO
GND
adjust
V
V
Y
YIO
REF
+
A
HA-2556
V
V
YIO
Y
This results in Equation 1, where X, Y and Z are high
impedance differential inputs
To accomplish this the differential input voltages are first
converted into differential currents by the X and Y input
transconductance stages. The currents are then scaled by a
constant reference and combined in the multiplier core. The
multiplier core is a basic Gilbert Cell that produces a
differential output current proportional to the product of X and
Y input signal currents. This current becomes the output for
the HA-2557.
The HA-2556 takes the output current of the core and feeds it
to a transimpedance amplifier, that converts the current to a
voltage. In the multiplier configuration, negative feedback is
provided with the Z transconductance amplifier by connecting
V
which is subtracted from the multiplier core before being
applied to the high gain transimpedance amp. The Z stage, by
virtue of it’s similarity to the X and Y stages, also cancels
V
-
B
OUT
OUT
V
Z
+
= Z
to the Z input. The Z stage converts V
-15V
V
=
NC
NC
NC
Y
FIGURE 1. DRIVING CAPACITIVE LOAD
+
X x Y
------------- -
V
5
V
BIAS
Z
-
1
2
3
4
5
6
7
8
REF
+
-
50Ω
V
Σ
CC
+
-
.
+
+
-
-
16
15
14
13
12
11
10
9
OUT
V+
V-
1kΩ
V
NC
NC
NC
V
Z
+15V
V
-
X
Z
+
+
OUT
to a current
V
20pF
April 29, 2008
OUT
FN2477.6
(EQ. 1)