AD9251 Analog Devices, AD9251 Datasheet - Page 8

• Manufacturer Part Number: AD9251
• Description: 14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9251

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9251
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
Timing Diagrams
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
CH A/CH B DATA
CH A/CH B DATA
DCOA/DCOB
DCOA/DCOB
CLK+
CLK–
CLK+
CLK–
VIN
VIN
Conditions
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
N – 1
N – 1
t
t
CH
CH
Figure 3. CMOS Interleaved Output Timing
Figure 2. CMOS Output Data Timing
t
t
PD
PD
N
N
t
t
t
t
CH A
N – 9
A
A
CLK
CLK
Rev. A | Page 8 of 36
t
t
DCO
DCO
t
t
N – 9
SKEW
SKEW
CH B
N – 9
N + 1
N + 1
CH A
N – 8
N – 8
CH B
N – 8
N + 2
N + 2
CH A
N – 7
N – 7
N + 3
N + 3
CH B
N – 7
CH A
N – 6
N – 6
Min
2
2
40
2
2
10
10
10
10
N + 4
N + 4
CH B
N – 6
CH A
N – 5
N – 5
Typ
0.24
0.40
N + 5
N + 5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns