AD9251 Analog Devices, AD9251 Datasheet - Page 30

• Manufacturer Part Number: AD9251
• Description: 14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9251

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9251
HARDWARE INTERFACE
The pins described in Table 13 constitute the physical interface
between the programming device of the user and the serial port
of the AD9251. The SCLK pin and the CSB pin function as
inputs when using the SPI interface. The SDIO pin is
bidirectional, functioning as an input during write phases and
as an output during readback.
The SPI interface is flexible enough to be controlled by
either FPGAs or microcontrollers. One method for SPI
configuration is described in detail in the
cation Note, Microcontroller-Based Serial Port Interface
(SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9251 to prevent these signals from transi-
tioning at the converter inputs during critical sampling periods.
SDIO/DCS and SCLK/DFS serve a dual function when the
SPI interface is not being used. When the pins are strapped to
AVDD or ground during device power-on, they are associated
with a specific function. The Digital Outputs section describes
the strappable functions supported on the AD9251.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the
PDWN pin serve as standalone CMOS-compatible control pins.
When the device is powered up, it is assumed that the user
intends to use the pins as static control lines for the duty cycle
stabilizer, output data format, output enable, and power-down
AN-812
Appli-
Rev. A | Page 30 of 36
feature control. In this mode, connect the CSB chip select to
AVDD, which disables the serial port interface.
Table 14. Mode Selection
Pin
SDIO/DCS
SCLK/DFS
OEB
PDWN
SPI ACCESSIBLE FEATURES
Table 15 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the
via SPI. The AD9251 part-specific features are described in
detail in Table 16.
Table 15. Features Accessible Using the SPI
Feature
Mode
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
AN-877
External
Voltage
AVDD (default)
AGND
AVDD
AGND (default)
AVDD
AGND (default)
AVDD
AGND (default)
Application Note, Interfacing to High Speed ADCs
Allows the user to vary the DCO delay
Description
Allows the user to set either power-down mode
or standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the
converter offset
Allows the user to set test modes to have known
data on output bits
Allows the user to set up outputs
Allows the user to set the output clock polarity
Configuration
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
Outputs in high impedance
Outputs enabled
Chip in power-down or standby
Normal operation