AD7291 Analog Devices, AD7291 Datasheet - Page 20

• Manufacturer Part Number: AD7291
• Description: 8-Channel, I2C, 12-Bit SAR ADC with Temperature Sensor
• Manufacturer: Analog Devices

Specifications of AD7291

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 22.2kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP

AD7291
HYSTERESIS REGISTER
Each analog input channel and the internal temperature sensor
has its own hysteresis register, which is a 16-bit read/write
register. Only the 12 LSBs are used. Bit D15 to Bit D12 are not
used in the register and are set to 0s. The hysteresis register
stores the hysteresis value, N, when using the limit registers.
Each pair of limit registers has a dedicated hysteresis register.
The hysteresis value determines the reset point for the ALERT
pin if a violation of the limits occurs. For example, if a hysteresis
value of eight LSBs is required on the upper and lower limits of
Channel 0, the 16-bit word, 0000 0000 0000 1000, should be
written to the hysteresis register of CH0, the address of which
is 0x06 (see Table 25 and Table 26). During power-up, the
hysteresis registers content defaults to all zeros (0x0000). If a
hysteresis value is required, that value must be written to the
hysteresis register for the channel in question.
Table 25. Hysteresis Register (First Read/Write Byte)
MSB
D15
0
Table 26. Hysteresis Register (Second Read/Write Byte)
D7
B7
Table 27. Alert Status Register A (First Read Byte)
D15
CH7
Table 28. Alert Status Register A (Second Read Byte)
D7
CH3
Table 29. Alert Status Register B (First Read Byte)
D15
0
Table 30. Alert Status Register B (Second Read Byte)
D7
0
HIGH
HIGH
D14
0
D6
B6
D6
0
D13
0
D5
B5
D14
CH7
D6
CH3
D14
0
LOW
LOW
D5
0
D12
0
D4
B4
D11
B11
D3
B3
D4
0
D13
CH6
D5
CH2
D13
0
HIGH
HIGH
D10
B10
D2
B2
D3
TSENSE_AVG
D9
B9
D1
B1
D12
CH6
D4
CH2
D12
0
LOW
LOW
HIGH
D8
B8
LSB
D0
B0
Rev. B | Page 20 of 28
D2
TSENSE_AVG
D11
CH5
D3
CH1
ALERT STATUS REGISTER A AND ALERT STATUS
REGISTER B (0x1F AND 0x20)
The alert status registers are 16-bit, read-only registers that
provide information on an alert event. If a conversion result
activates the ALERT pin, as described in the Limit Registers
(0x04 to 0x1E) section, the alert status register can be read to
gain further information. There are two alert status registers in
the AD7291; Alert Status Register A, which stores alerts for the
analog voltage conversion channels (see Table 27 and Table 28)
and Alert Status Register B, which stores alerts for the internal
temperature sensor only (see Table 29 and Table 30).
Both alert status registers contain two status bits per channel,
one corresponding to the DATA
DATA
violation occurred—that is, on which channel—and whether
the violation occurred on the upper or lower limit. If a second
alert event occurs on the other channel between receiving the
first alert and interrogating the alert status register, the corres-
ponding bit for that alert event is also set. The entire contents
of the alert status register can be cleared by writing 1 to Bit D2
in the command register.
For example, if Bit D14 in Alert Status Register A is set to 1, the
lower limit on Channel 7 (Register 0x1A) has been violated,
while if Bit D11 is set 1, the upper limit on Channel 5 has been
violated (Register 0x13).
The TSENSE
by comparison with the T
0x1C). Likewise, the TSENSE
are determined by comparison with the T
(Register 0x1D).
D11
0
HIGH
HIGH
LOW
LOW
limit. The bit with a status of 1 shows where the
HIGH
D10
CH5
D2
CH1
D1
TSENSE
and TSENSE_AVG
D10
0
LOW
LOW
HIGH
SENSE
LOW
DATA
D9
CH4
D1
CH0
HIGH
and TSENSE_AVG
HIGH
HIGH
limit and the other to the
HIGH
HIGH
D9
0
alerts are determined
register (Register
SENSE
D0
TSENSE
DATA
Data Sheet
LOW
D8
CH4
D0
CH0
D8
0
LOW
LOW
LOW
LOW
alerts
register