AD7291 Analog Devices, AD7291 Datasheet - Page 19

• Manufacturer Part Number: AD7291
• Description: 8-Channel, I2C, 12-Bit SAR ADC with Temperature Sensor
• Manufacturer: Analog Devices

Specifications of AD7291

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 22.2kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP

Data Sheet
Table 17. T
MSB
D15
ADD3
Table 18. T
D7
B7
T
The T
used to store the average result from the internal temperature
sensor. This register stores the average temperature readings
from the ADC in an 11-bit twos complement format, D11 to
D0, and uses Bit D15 to Bit D12 to store the channel address
bits. The T
T
conversion result given by the AD7291 after averaging is
enabled is the actual first T
details the temperature data format, which applies to the
internal temperature sensor. See the Temperature Sensor
Averaging section for more details.
Table 19. T
MSB
D15
ADD3
Table 20. T
D7
B7
LIMIT REGISTERS (0x04 TO 0x1E)
The AD7291 has nine pairs of limit registers. Each pair stores
high and low conversion limits for each analog input channel
and the internal temperature sensor. Each pair of limit registers
has one associated hysteresis register. All 27 registers are 16 bits
wide; only the 12 LSBs of the registers are used for the AD7291.
The four MSBs, D15 and D12, in these registers should contain
0s. During power-up, the contents of the DATA
each analog voltage channel is full scale (0x0FFF), while the
default contents of the DATA
zero scale (0x0000). The output coding of the AD7291 is twos
complement for the temperature conversion result. The default
content for the T
default content of the T
AD7291 signals an alert in hardware if the conversion result
moves outside the upper or lower limit set by the limit registers.
SENSE
SENSE
SENSE
conversion is completed. The first T
AVERAGE RESULT REGISTER (0x03)
D14
ADD2
D14
ADD2
D6
B6
D6
B6
average result register is a 16-bit read-only register
SENSE
SENSE
SENSE
SENSE
SENSE
average result register is updated after every
Conversion Result Register (First Read)
Result Register (Second Read)
Average Result Register (First Read)
Average Result Register (Second Read)
SENSE
D5
B5
D5
B5
D13
ADD1
D13
ADD1
DATA
SENSE
D4
B4
D4
B4
SENSE
HIGH
DATA
D12
ADD0
D12
ADD0
LOW
conversion result. Table 13
register is 0x07FF, while the
voltage channels registers is
D3
B3
D3
B3
LOW
D11
B11
D11
B11
register is 0x0800. The
D2
B2
D2
B2
SENSE
D10
B10
D10
B10
average
HIGH
D1
B1
D1
B1
register for
D9
B9
D9
B9
LSB
D0
B0
LSB
D0
B0
D8
B8
D8
B8
Rev. B | Page 19 of 28
DATA
The DATA
temperature sensor are 16-bit read/write registers; only the
12 LSBs of each register are used. Bit D15 to Bit D12 are not
used in the register and are set to 0s. This register stores the
upper limit that activates the ALERT output. If the value in the
conversion result register is greater than the value in the
DATA
the conversion result returns to a value at least N LSBs below
the DATA
value of N is taken from the hysteresis register associated with
that channel. The ALERT pin can also be reset by writing to
Bit D2 in the command register.
Table 21. DATA
MSB
D15
0
Table 22. DATA
D7
B7
DATA
The DATA
register; only the 12 LSBs of each register are used. Bit D15 to
Bit D12 are not used in the register and are set to 0s. The
register stores the lower limit that activates the ALERT output.
If the value in the T
the value in the DATA
channel. When the conversion result returns to a value at least
N LSBs above the DATA
pin is reset. The value of N is taken from the hysteresis register
associated with that channel. The ALERT output pin can also be
reset by writing to Bit D2 in the command register.
Table 23. DATA
MSB
D15
0
Table 24. DATA
D7
B7
HIGH
HIGH
LOW
D14
0
D6
B6
D14
0
D6
B6
HIGH
Register
Register
register, an ALERT occurs for that channel. When
HIGH
LOW
register value, the ALERT output pin is reset. The
register for each channel is a 16-bit read/write
registers for CH0 to CH7 and the internal
D13
0
D5
B5
D13
0
D5
B5
HIGH
HIGH
LOW
LOW
SENSE
Register (First Read/Write)
Register (Second Read/Write)
Register (First Read/Write)
Register (Second Read/Write)
LOW
conversion result register is less than
LOW
D12
0
D4
B4
D12
0
D4
B4
register, an ALERT occurs for that
register value, the ALERT output
D11
B11
D3
B3
D11
B11
D3
B3
D10
B10
D2
B2
D10
B10
D2
B2
D9
D9
B9
B1
B9
D1
B1
D1
AD7291
D8
B8
LSB
D0
B0
D8
B8
LSB
D0
B0